From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FC1FC2D0DB for ; Mon, 20 Jan 2020 17:44:47 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id DE61122525 for ; Mon, 20 Jan 2020 17:44:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="w7FpMoXj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DE61122525 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 719DB4AF38; Mon, 20 Jan 2020 12:44:46 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Authentication-Results: mm01.cs.columbia.edu (amavisd-new); dkim=softfail (fail, message has been altered) header.i=@kernel.org Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tJcNSB8Lsyn5; Mon, 20 Jan 2020 12:44:41 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 834804AF39; Mon, 20 Jan 2020 12:44:41 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 98D774AF37 for ; Mon, 20 Jan 2020 12:44:40 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 86-67GE98zOB for ; Mon, 20 Jan 2020 12:44:38 -0500 (EST) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 90C4D4AEB2 for ; Mon, 20 Jan 2020 12:44:38 -0500 (EST) Received: from willie-the-truck (236.31.169.217.in-addr.arpa [217.169.31.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4724122525; Mon, 20 Jan 2020 17:44:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1579542277; bh=LagBF9JsoTc8+nyOltAMAYejmrgZJ3mO+mVxPeC8f1w=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=w7FpMoXjz/7pumqEKrdLw5EkzFDm7uZCVrCeu9f6zKvsAihTEUpnLcuSyqJ2D0lPB FJ9mdYdDQgRjDsWT4AR9Z3CDQ385P3rodouQHK7lXg/k8NNWwe6Vgf9xz8zdE+sVXq FxT2MsSp2f7eJ4oki/D8hvagynM2fMR0DfryegYQ= Date: Mon, 20 Jan 2020 17:44:33 +0000 From: Will Deacon To: Andrew Murray Subject: Re: [PATCH v3 2/3] KVM: arm64: limit PMU version to ARMv8.4 Message-ID: <20200120174432.GA23090@willie-the-truck> References: <20200102123905.29360-1-andrew.murray@arm.com> <20200102123905.29360-3-andrew.murray@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200102123905.29360-3-andrew.murray@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) Cc: Catalin Marinas , Marc Zyngier , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Thu, Jan 02, 2020 at 12:39:04PM +0000, Andrew Murray wrote: > ARMv8.5-PMU introduces 64-bit event counters, however KVM doesn't yet > support this. Let's trap the Debug Feature Registers in order to limit > PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.4. > > Signed-off-by: Andrew Murray > Reviewed-by: Suzuki K Poulose > --- > arch/arm64/include/asm/sysreg.h | 4 ++++ > arch/arm64/kvm/sys_regs.c | 36 +++++++++++++++++++++++++++++++-- > 2 files changed, 38 insertions(+), 2 deletions(-) I'll need an ack from the kvm side for this. > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 6e919fafb43d..1b74f275a115 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -672,6 +672,10 @@ > #define ID_AA64DFR0_TRACEVER_SHIFT 4 > #define ID_AA64DFR0_DEBUGVER_SHIFT 0 > > +#define ID_DFR0_PERFMON_SHIFT 24 > + > +#define ID_DFR0_EL1_PMUVER_8_4 5 > + > #define ID_ISAR5_RDM_SHIFT 24 > #define ID_ISAR5_CRC32_SHIFT 16 > #define ID_ISAR5_SHA2_SHIFT 12 > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 9f2165937f7d..61b984d934d1 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -668,6 +668,37 @@ static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) > return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); > } > > +static bool access_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + struct sys_reg_params *p, > + const struct sys_reg_desc *rd) > +{ > + if (p->is_write) > + return write_to_read_only(vcpu, p, rd); > + > + /* Limit guests to PMUv3 for ARMv8.4 */ > + p->regval = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); > + p->regval = cpuid_feature_cap_signed_field_width(p->regval, > + ID_AA64DFR0_PMUVER_SHIFT, > + 4, ID_DFR0_EL1_PMUVER_8_4); nit: I'd probably have a separate define for the field value of the 64-bit register, since there's no guarantee other values will be encoded the same way. (i.e. add ID_AA64DFR0_PMUVER_8_4 as well). > + > + return p->regval; > +} > + > +static bool access_id_dfr0_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > + const struct sys_reg_desc *rd) > +{ > + if (p->is_write) > + return write_to_read_only(vcpu, p, rd); > + > + /* Limit guests to PMUv3 for ARMv8.4 */ > + p->regval = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1); > + p->regval = cpuid_feature_cap_signed_field_width(p->regval, You could just return the result here (same above). Will _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm