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From: Robert Richter <rrichter@marvell.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	linux-kernel@vger.kernel.org,
	Andrew Murray <Andrew.Murray@arm.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v3 03/32] irqchip/gic-v3: Workaround Cavium TX1 erratum when reading GICD_TYPER2
Date: Wed, 11 Mar 2020 09:45:15 +0100
Message-ID: <20200311084515.5vbfudbls3cj2cre@rric.localdomain> (raw)
In-Reply-To: <b1b7db1f0e1c47b7d9e2dfbbe3409b77@kernel.org>

Hi Marc,

On 10.03.20 11:41:09, Marc Zyngier wrote:
> On 2020-03-09 22:11, Robert Richter wrote:
> > On 24.12.19 11:10:26, Marc Zyngier wrote:

> > > @@ -1502,6 +1512,12 @@ static const struct gic_quirk gic_quirks[] = {
> > >  		.mask	= 0xffffffff,
> > >  		.init	= gic_enable_quirk_hip06_07,
> > >  	},
> > > +	{
> > > +		.desc	= "GICv3: Cavium TX1 GICD_TYPER2 erratum",
> > 
> > There is no errata number yet.
> 
> Please let me know when/if you obtain one.

GIC-38539: GIC faults when accessing reserved GICD_TYPER2 register

Applies to (covered with iidr mask below):

 ThunderX: CN88xx
 OCTEON TX: CN83xx, CN81xx
 OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*

Issue: Access to GIC reserved registers results in an exception.
Notes:
1) This applies to other reserved registers too.
2) The errata number is unique over all IP blocks, so a macro
   CAVIUM_ERRATUM_38539 is ok.

> 
> > 
> > > +		.iidr	= 0xa100034c,
> > > +		.mask	= 0xfff00fff,
> > > +		.init	= gic_enable_quirk_tx1,
> > 
> > All TX1 and OcteonTX parts are affected, which is a0-a7 and b0-b7. So
> > the iidr/mask should be:
> > 
> > 		.iidr   = 0xa000034c,
> > 		.mask   = 0xe8f00fff,
> 
> Thanks, that's pretty helpful. I'll update the patch with these values
> and the corresponding description.
> 
> > > +	},
> > >  	{
> > >  	}
> > >  };

Thank you for addressing this.

-Robert
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  parent reply index

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-24 11:10 [PATCH v3 00/32] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 01/32] irqchip/gic-v3: Detect GICv4.1 supporting RVPEID Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 02/32] irqchip/gic-v3: Add GICv4.1 VPEID size discovery Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 03/32] irqchip/gic-v3: Workaround Cavium TX1 erratum when reading GICD_TYPER2 Marc Zyngier
2020-03-09 22:11   ` Robert Richter
2020-03-10 11:41     ` Marc Zyngier
2020-03-10 12:34       ` Robert Richter
2020-03-11  8:45       ` Robert Richter [this message]
2020-03-11  9:03         ` Marc Zyngier
2020-03-11  9:18           ` Robert Richter
2019-12-24 11:10 ` [PATCH v3 04/32] irqchip/gic-v3: Use SGIs without active state if offered Marc Zyngier
2019-12-28  8:56   ` Zenghui Yu
2019-12-28 10:36     ` Marc Zyngier
2019-12-30  3:50       ` Zenghui Yu
2019-12-24 11:10 ` [PATCH v3 05/32] irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation Marc Zyngier
2020-01-20 14:03   ` Zenghui Yu
2020-01-20 15:11     ` Marc Zyngier
2020-01-22  2:59   ` Zenghui Yu
2019-12-24 11:10 ` [PATCH v3 06/32] irqchip/gic-v4.1: Implement the v4.1 flavour of VMAPP Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 07/32] irqchip/gic-v4.1: Don't use the VPE proxy if RVPEID is set Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 08/32] irqchip/gic-v4.1: Implement the v4.1 flavour of VMOVP Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 09/32] irqchip/gic-v4.1: Plumb skeletal VPE irqchip Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 10/32] irqchip/gic-v4.1: Add mask/unmask doorbell callbacks Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 11/32] irqchip/gic-v4.1: Add VPE residency callback Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 12/32] irqchip/gic-v4.1: Add VPE eviction callback Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 13/32] irqchip/gic-v4.1: Add VPE INVALL callback Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 14/32] irqchip/gic-v4.1: Suppress per-VLPI doorbell Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 15/32] irqchip/gic-v4.1: Allow direct invalidation of VLPIs Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 16/32] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 17/32] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 18/32] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 19/32] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 20/32] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 21/32] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 22/32] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 23/32] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 24/32] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 25/32] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 26/32] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 27/32] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 28/32] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier
2019-12-28  9:19   ` Zenghui Yu
2019-12-28 10:41     ` Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 29/32] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts Marc Zyngier
2020-01-15  2:49   ` Shaokun Zhang
2020-01-15  3:49     ` Zenghui Yu
2020-01-15 13:32       ` Marc Zyngier
2020-01-15 13:49         ` Zenghui Yu
2020-01-16  6:13         ` Shaokun Zhang
2020-01-15 13:17     ` Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 30/32] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 31/32] KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable Marc Zyngier
2019-12-24 11:10 ` [PATCH v3 32/32] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier

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