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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: kernel-team@android.com, Will Deacon <will@kernel.org>,
	Andre Przywara <andre.przywara@arm.com>,
	Dave Martin <Dave.Martin@arm.com>,
	George Cherian <gcherian@marvell.com>,
	"Zengtao \(B\)" <prime.zeng@hisilicon.com>,
	Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH v2 04/17] arm64: Add level-hinted TLB invalidation helper
Date: Mon, 15 Jun 2020 14:27:06 +0100	[thread overview]
Message-ID: <20200615132719.1932408-5-maz@kernel.org> (raw)
In-Reply-To: <20200615132719.1932408-1-maz@kernel.org>

Add a level-hinted TLB invalidation helper that only gets used if
ARMv8.4-TTL gets detected.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/stage2_pgtable.h |  9 +++++
 arch/arm64/include/asm/tlbflush.h       | 45 +++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h
index b767904f28b1..996bf98f0cab 100644
--- a/arch/arm64/include/asm/stage2_pgtable.h
+++ b/arch/arm64/include/asm/stage2_pgtable.h
@@ -256,4 +256,13 @@ stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)
 	return (boundary - 1 < end - 1) ? boundary : end;
 }
 
+/*
+ * Level values for the ARMv8.4-TTL extension, mapping PUD/PMD/PTE and
+ * the architectural page-table level.
+ */
+#define S2_NO_LEVEL_HINT	0
+#define S2_PUD_LEVEL		1
+#define S2_PMD_LEVEL		2
+#define S2_PTE_LEVEL		3
+
 #endif	/* __ARM64_S2_PGTABLE_H_ */
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index bc3949064725..e05c31fd0bbc 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -10,6 +10,7 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/bitfield.h>
 #include <linux/mm_types.h>
 #include <linux/sched.h>
 #include <asm/cputype.h>
@@ -59,6 +60,50 @@
 		__ta;						\
 	})
 
+/*
+ * Level-based TLBI operations.
+ *
+ * When ARMv8.4-TTL exists, TLBI operations take an additional hint for
+ * the level at which the invalidation must take place. If the level is
+ * wrong, no invalidation may take place. In the case where the level
+ * cannot be easily determined, a 0 value for the level parameter will
+ * perform a non-hinted invalidation.
+ *
+ * For Stage-2 invalidation, use the level values provided to that effect
+ * in asm/stage2_pgtable.h.
+ */
+#define TLBI_TTL_MASK		GENMASK_ULL(47, 44)
+#define TLBI_TTL_PS_4K		1
+#define TLBI_TTL_PS_16K		2
+#define TLBI_TTL_PS_64K		3
+
+#define __tlbi_level(op, addr, level)					\
+	do {								\
+		u64 arg = addr;						\
+									\
+		if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) &&	\
+		    level) {						\
+			u64 ttl = level & 3;				\
+									\
+			switch (PAGE_SIZE) {				\
+			case SZ_4K:					\
+				ttl |= TLBI_TTL_PS_4K << 2;		\
+				break;					\
+			case SZ_16K:					\
+				ttl |= TLBI_TTL_PS_16K << 2;		\
+				break;					\
+			case SZ_64K:					\
+				ttl |= TLBI_TTL_PS_64K << 2;		\
+				break;					\
+			}						\
+									\
+			arg &= ~TLBI_TTL_MASK;				\
+			arg |= FIELD_PREP(TLBI_TTL_MASK, ttl);		\
+		}							\
+									\
+		__tlbi(op, arg);					\
+	} while(0)
+
 /*
  *	TLB Invalidation
  *	================
-- 
2.27.0

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  parent reply	other threads:[~2020-06-15 13:27 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-15 13:27 [PATCH v2 00/17] KVM: arm64: Preliminary NV patches Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 01/17] KVM: arm64: Factor out stage 2 page table data from struct kvm Marc Zyngier
2020-06-16 15:59   ` Alexandru Elisei
2020-06-16 16:18     ` Marc Zyngier
2020-06-17 12:58       ` Alexandru Elisei
2020-06-25 12:19       ` Alexandru Elisei
2020-07-06 12:17         ` Marc Zyngier
2020-07-06 15:49           ` Alexandru Elisei
2020-06-17 12:40   ` Marc Zyngier
2020-06-25 12:49   ` Alexandru Elisei
2020-07-13  9:47   ` Andrew Scull
2020-07-13 14:20     ` Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 02/17] arm64: Detect the ARMv8.4 TTL feature Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 03/17] arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors Marc Zyngier
2020-06-15 13:27 ` Marc Zyngier [this message]
2020-06-25 16:24   ` [PATCH v2 04/17] arm64: Add level-hinted TLB invalidation helper Alexandru Elisei
2020-06-15 13:27 ` [PATCH v2 05/17] KVM: arm64: Use TTL hint in when invalidating stage-2 translations Marc Zyngier
2020-06-26 13:14   ` Alexandru Elisei
2020-06-15 13:27 ` [PATCH v2 06/17] KVM: arm64: Introduce accessor for ctxt->sys_reg Marc Zyngier
2020-06-26 15:39   ` Alexandru Elisei
2020-07-06 12:15     ` Marc Zyngier
2020-07-06 12:35       ` Alexandru Elisei
2020-06-15 13:27 ` [PATCH v2 07/17] KVM: arm64: hyp: Use ctxt_sys_reg/__vcpu_sys_reg instead of raw sys_regs access Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 08/17] KVM: arm64: sve: Use __vcpu_sys_reg() " Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 09/17] KVM: arm64: pauth: Use ctxt_sys_reg() " Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 10/17] KVM: arm64: debug: " Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 11/17] KVM: arm64: Make struct kvm_regs userspace-only Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 12/17] KVM: arm64: Move ELR_EL1 to the system register array Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 13/17] KVM: arm64: Move SP_EL1 " Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 14/17] KVM: arm64: Disintegrate SPSR array Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 15/17] KVM: arm64: Move SPSR_EL1 to the system register array Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 16/17] KVM: arm64: timers: Rename kvm_timer_sync_hwstate to kvm_timer_sync_user Marc Zyngier
2020-06-15 13:27 ` [PATCH v2 17/17] KVM: arm64: timers: Move timer registers to the sys_regs file Marc Zyngier

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