From: Andrew Jones <drjones@redhat.com> To: Jingyi Wang <wangjingyi11@huawei.com> Cc: kvm@vger.kernel.org, maz@kernel.org, prime.zeng@hisilicon.com, kvmarm@lists.cs.columbia.edu Subject: Re: [kvm-unit-tests PATCH v3 08/10] arm64: microbench: Add vtimer latency test Date: Sat, 1 Aug 2020 18:22:41 +0200 [thread overview] Message-ID: <20200801162241.enpfjfl5ykkowchf@kamzik.brq.redhat.com> (raw) In-Reply-To: <20200731074244.20432-9-wangjingyi11@huawei.com> On Fri, Jul 31, 2020 at 03:42:42PM +0800, Jingyi Wang wrote: > Trigger PPIs by setting up a 10msec timer and test the latency. > > Signed-off-by: Jingyi Wang <wangjingyi11@huawei.com> > --- > arm/micro-bench.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 52 insertions(+), 1 deletion(-) > > diff --git a/arm/micro-bench.c b/arm/micro-bench.c > index 09d9d53..1e1bde5 100644 > --- a/arm/micro-bench.c > +++ b/arm/micro-bench.c > @@ -21,8 +21,10 @@ > #include <libcflat.h> > #include <asm/gic.h> > #include <asm/gic-v3-its.h> > +#include <asm/timer.h> > > #define NS_5_SECONDS (5 * 1000 * 1000 * 1000UL) > + > static u32 cntfrq; > > static volatile bool irq_ready, irq_received; > @@ -33,9 +35,16 @@ static void (*write_eoir)(u32 irqstat); > > static void gic_irq_handler(struct pt_regs *regs) > { > + u32 irqstat = gic_read_iar(); > irq_ready = false; > irq_received = true; > - gic_write_eoir(gic_read_iar()); > + gic_write_eoir(irqstat); > + > + if (irqstat == PPI(TIMER_VTIMER_IRQ)) { > + write_sysreg((ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE), > + cntv_ctl_el0); > + isb(); > + } > irq_ready = true; > } > > @@ -198,6 +207,47 @@ static void lpi_exec(void) > assert_msg(irq_received, "failed to receive LPI in time, but received %d successfully\n", received); > } > > +static bool timer_prep(void) > +{ > + static void *gic_isenabler; This doesn't need to be static. > + > + gic_enable_defaults(); > + install_irq_handler(EL1H_IRQ, gic_irq_handler); > + local_irq_enable(); > + > + gic_isenabler = gicv3_sgi_base() + GICR_ISENABLER0; We can't assume GICv3. This test also runs with GICv2. I'll fix this up myself. Thanks, drew > + writel(1 << PPI(TIMER_VTIMER_IRQ), gic_isenabler); > + write_sysreg(ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0); > + isb(); > + > + gic_prep_common(); > + return true; > +} > + > +static void timer_exec(void) > +{ > + u64 before_timer; > + u64 timer_10ms; > + unsigned tries = 1 << 28; > + static int received = 0; > + > + irq_received = false; > + > + before_timer = read_sysreg(cntvct_el0); > + timer_10ms = cntfrq / 100; > + write_sysreg(before_timer + timer_10ms, cntv_cval_el0); > + write_sysreg(ARCH_TIMER_CTL_ENABLE, cntv_ctl_el0); > + isb(); > + > + while (!irq_received && tries--) > + cpu_relax(); > + > + if (irq_received) > + ++received; > + > + assert_msg(irq_received, "failed to receive PPI in time, but received %d successfully\n", received); > +} > + > static void hvc_exec(void) > { > asm volatile("mov w0, #0x4b000000; hvc #0" ::: "w0"); > @@ -245,6 +295,7 @@ static struct exit_test tests[] = { > {"ipi", ipi_prep, ipi_exec, 65536, true}, > {"ipi_hw", ipi_hw_prep, ipi_exec, 65536, true}, > {"lpi", lpi_prep, lpi_exec, 65536, true}, > + {"timer_10ms", timer_prep, timer_exec, 256, true}, > }; > > struct ns_time { > -- > 2.19.1 > > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
next prev parent reply other threads:[~2020-08-01 16:22 UTC|newest] Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-31 7:42 [kvm-unit-tests PATCH v3 00/10] arm/arm64: Add IPI/LPI/vtimer " Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 01/10] arm64: microbench: get correct ipi received num Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 02/10] arm64: microbench: Generalize ipi test names Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 03/10] arm64: microbench: gic: Add ipi latency test for gicv4.1 support kvm Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 04/10] arm64: its: Handle its command queue wrapping Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 05/10] arm64: microbench: its: Add LPI latency test Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 06/10] arm64: microbench: Allow each test to specify its running times Jingyi Wang 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 07/10] arm64: microbench: Add time limit for each individual test Jingyi Wang 2020-08-01 16:13 ` Andrew Jones 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 08/10] arm64: microbench: Add vtimer latency test Jingyi Wang 2020-08-01 16:22 ` Andrew Jones [this message] 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 09/10] arm64: microbench: Add test->post() to further process test results Jingyi Wang 2020-08-01 17:03 ` Andrew Jones 2020-07-31 7:42 ` [kvm-unit-tests PATCH v3 10/10] arm64: microbench: Add timer_post() to get actual PPI latency Jingyi Wang 2020-07-31 12:01 ` [kvm-unit-tests PATCH v3 00/10] arm/arm64: Add IPI/LPI/vtimer latency test Andrew Jones 2020-08-03 2:15 ` Jingyi Wang 2020-08-01 17:40 ` Andrew Jones 2020-08-05 11:54 ` Jingyi Wang 2020-08-05 12:13 ` Marc Zyngier 2020-08-11 1:48 ` Jingyi Wang 2020-08-11 7:49 ` Marc Zyngier 2020-08-17 1:46 ` Jingyi Wang 2020-08-17 8:26 ` Marc Zyngier
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