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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org
Cc: Prasad Sodagudi <psodagud@codeaurora.org>,
	Srinivas Ramana <sramana@codeaurora.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Ajay Patil <pajay@qti.qualcomm.com>,
	kernel-team@android.com, Will Deacon <will@kernel.org>,
	Ard Biesheuvel <ardb@kernel.org>
Subject: [PATCH v5 07/21] arm64: Simplify init_el2_state to be non-VHE only
Date: Mon, 25 Jan 2021 10:50:05 +0000
Message-ID: <20210125105019.2946057-8-maz@kernel.org> (raw)
In-Reply-To: <20210125105019.2946057-1-maz@kernel.org>

As init_el2_state is now nVHE only, let's simplify it and drop
the VHE setup.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: David Brazdil <dbrazdil@google.com>
---
 arch/arm64/include/asm/el2_setup.h | 36 +++++++-----------------------
 arch/arm64/kernel/head.S           |  2 +-
 arch/arm64/kvm/hyp/nvhe/hyp-init.S |  2 +-
 3 files changed, 10 insertions(+), 30 deletions(-)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 540116de80bf..d77d358f9395 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -32,16 +32,14 @@
  * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in
  * EL2.
  */
-.macro __init_el2_timers mode
-.ifeqs "\mode", "nvhe"
+.macro __init_el2_timers
 	mrs	x0, cnthctl_el2
 	orr	x0, x0, #3			// Enable EL1 physical timers
 	msr	cnthctl_el2, x0
-.endif
 	msr	cntvoff_el2, xzr		// Clear virtual offset
 .endm
 
-.macro __init_el2_debug mode
+.macro __init_el2_debug
 	mrs	x1, id_aa64dfr0_el1
 	sbfx	x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4
 	cmp	x0, #1
@@ -55,7 +53,6 @@
 	ubfx	x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4
 	cbz	x0, .Lskip_spe_\@		// Skip if SPE not present
 
-.ifeqs "\mode", "nvhe"
 	mrs_s	x0, SYS_PMBIDR_EL1              // If SPE available at EL2,
 	and	x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT)
 	cbnz	x0, .Lskip_spe_el2_\@		// then permit sampling of physical
@@ -66,10 +63,6 @@
 	mov	x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)
 	orr	x2, x2, x0			// If we don't have VHE, then
 						// use EL1&0 translation.
-.else
-	orr	x2, x2, #MDCR_EL2_TPMS		// For VHE, use EL2 translation
-						// and disable access from EL1
-.endif
 
 .Lskip_spe_\@:
 	msr	mdcr_el2, x2			// Configure debug traps
@@ -145,37 +138,24 @@
 
 /**
  * Initialize EL2 registers to sane values. This should be called early on all
- * cores that were booted in EL2.
+ * cores that were booted in EL2. Note that everything gets initialised as
+ * if VHE was not evailable. The kernel context will be upgraded to VHE
+ * if possible later on in the boot process
  *
  * Regs: x0, x1 and x2 are clobbered.
  */
-.macro init_el2_state mode
-.ifnes "\mode", "vhe"
-.ifnes "\mode", "nvhe"
-.error "Invalid 'mode' argument"
-.endif
-.endif
-
+.macro init_el2_state
 	__init_el2_sctlr
-	__init_el2_timers \mode
-	__init_el2_debug \mode
+	__init_el2_timers
+	__init_el2_debug
 	__init_el2_lor
 	__init_el2_stage2
 	__init_el2_gicv3
 	__init_el2_hstr
-
-	/*
-	 * When VHE is not in use, early init of EL2 needs to be done here.
-	 * When VHE _is_ in use, EL1 will not be used in the host and
-	 * requires no configuration, and all non-hyp-specific EL2 setup
-	 * will be done via the _EL1 system register aliases in __cpu_setup.
-	 */
-.ifeqs "\mode", "nvhe"
 	__init_el2_nvhe_idregs
 	__init_el2_nvhe_cptr
 	__init_el2_nvhe_sve
 	__init_el2_nvhe_prepare_eret
-.endif
 .endm
 
 #endif /* __ARM_KVM_INIT_H__ */
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 07445fd976ef..36212c05df42 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -501,7 +501,7 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
 	msr	hcr_el2, x0
 	isb
 
-	init_el2_state nvhe
+	init_el2_state
 
 	/* Hypervisor stub */
 	adr_l	x0, __hyp_stub_vectors
diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/hyp-init.S
index 31b060a44045..222cfc3e7190 100644
--- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S
+++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S
@@ -189,7 +189,7 @@ SYM_CODE_START_LOCAL(__kvm_hyp_init_cpu)
 2:	msr	SPsel, #1			// We want to use SP_EL{1,2}
 
 	/* Initialize EL2 CPU state to sane values. */
-	init_el2_state nvhe			// Clobbers x0..x2
+	init_el2_state				// Clobbers x0..x2
 
 	/* Enable MMU, set vectors and stack. */
 	mov	x0, x28
-- 
2.29.2

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  parent reply index

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-25 10:49 [PATCH v5 00/21] arm64: Early CPU feature override, and applications to VHE, BTI and PAuth Marc Zyngier
2021-01-25 10:49 ` [PATCH v5 01/21] arm64: Fix labels in el2_setup macros Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 02/21] arm64: Fix outdated TCR setup comment Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 03/21] arm64: Turn the MMU-on sequence into a macro Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 04/21] arm64: Provide an 'upgrade to VHE' stub hypercall Marc Zyngier
2021-01-25 12:13   ` Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 05/21] arm64: Initialise as nVHE before switching to VHE Marc Zyngier
2021-01-25 12:13   ` Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 06/21] arm64: Move VHE-specific SPE setup to mutate_to_vhe() Marc Zyngier
2021-01-25 12:14   ` Catalin Marinas
2021-01-25 10:50 ` Marc Zyngier [this message]
2021-01-25 12:14   ` [PATCH v5 07/21] arm64: Simplify init_el2_state to be non-VHE only Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 08/21] arm64: Move SCTLR_EL1 initialisation to EL-agnostic code Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 09/21] arm64: cpufeature: Add global feature override facility Marc Zyngier
2021-01-25 12:15   ` Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 10/21] arm64: cpufeature: Use IDreg override in __read_sysreg_by_encoding() Marc Zyngier
2021-01-25 12:19   ` Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 11/21] arm64: Extract early FDT mapping from kaslr_early_init() Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 12/21] arm64: cpufeature: Add an early command-line cpufeature override facility Marc Zyngier
2021-01-25 18:37   ` Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 13/21] arm64: Allow ID_AA64MMFR1_EL1.VH to be overridden from the command line Marc Zyngier
2021-01-25 13:15   ` Suzuki K Poulose
2021-01-25 13:55     ` Marc Zyngier
2021-01-25 18:37   ` Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 14/21] arm64: Honor VHE being disabled from the command-line Marc Zyngier
2021-01-25 18:38   ` Catalin Marinas
2021-01-25 10:50 ` [PATCH v5 15/21] arm64: Add an aliasing facility for the idreg override Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 16/21] arm64: Make kvm-arm.mode={nvhe, protected} an alias of id_aa64mmfr1.vh=0 Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 17/21] KVM: arm64: Document HVC_VHE_RESTART stub hypercall Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 18/21] arm64: Move "nokaslr" over to the early cpufeature infrastructure Marc Zyngier
2021-01-25 12:54   ` Ard Biesheuvel
2021-01-25 13:54     ` Marc Zyngier
2021-01-25 14:19       ` Ard Biesheuvel
2021-01-25 14:28         ` Marc Zyngier
2021-01-25 15:00           ` Ard Biesheuvel
2021-01-25 10:50 ` [PATCH v5 19/21] arm64: cpufeatures: Allow disabling of BTI from the command-line Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 20/21] arm64: Defer enabling pointer authentication on boot core Marc Zyngier
2021-01-25 10:50 ` [PATCH v5 21/21] arm64: cpufeatures: Allow disabling of Pointer Auth from the command-line Marc Zyngier

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