From: Suzuki Kuruppassery Poulose <suzuki.poulose@arm.com>
To: Andrew Murray <andrew.murray@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 3/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters
Date: Wed, 11 Dec 2019 17:28:54 +0000 [thread overview]
Message-ID: <314c8b5e-5f12-63f9-0937-602450db70b2@arm.com> (raw)
In-Reply-To: <20191210120146.2942-4-andrew.murray@arm.com>
On 10/12/2019 12:01, Andrew Murray wrote:
> At present ARMv8 event counters are limited to 32-bits, though by
> using the CHAIN event it's possible to combine adjacent counters to
> achieve 64-bits. The perf config1:0 bit can be set to use such a
> configuration.
>
> With the introduction of ARMv8.5-PMU support, all event counters can
> now be used as 64-bit counters.
>
> Let's enable 64-bit event counters where support exists. Unless the
> user sets config1:0 we will adjust the counter value such that it
> overflows upon 32-bit overflow. This follows the same behaviour as
> the cycle counter which has always been (and remains) 64-bits.
>
> Signed-off-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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prev parent reply other threads:[~2019-12-11 17:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-10 12:01 [PATCH v2 0/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters Andrew Murray
2019-12-10 12:01 ` [PATCH v2 1/3] arm64: cpufeature: Extract capped fields Andrew Murray
2019-12-11 15:20 ` Suzuki Kuruppassery Poulose
2019-12-10 12:01 ` [PATCH v2 2/3] KVM: arm64: limit PMU version to ARMv8.4 Andrew Murray
2019-12-11 17:28 ` Suzuki Kuruppassery Poulose
2019-12-10 12:01 ` [PATCH v2 3/3] arm64: perf: Add support for ARMv8.5-PMU 64-bit counters Andrew Murray
2019-12-11 17:28 ` Suzuki Kuruppassery Poulose [this message]
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