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Wed, 20 Nov 2019 10:18:21 +0000 (UTC) Received: from [10.36.116.37] (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 694F71968D; Wed, 20 Nov 2019 10:18:14 +0000 (UTC) Subject: Re: [PATCH v9 00/11] SMMUv3 Nested Stage Setup (VFIO part) To: Tomasz Nowicki , "eric.auger.pro@gmail.com" , "iommu@lists.linux-foundation.org" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , "kvmarm@lists.cs.columbia.edu" , "joro@8bytes.org" , "alex.williamson@redhat.com" , "jacob.jun.pan@linux.intel.com" , "yi.l.liu@intel.com" , "jean-philippe.brucker@arm.com" , "will.deacon@arm.com" , "robin.murphy@arm.com" References: <20190711135625.20684-1-eric.auger@redhat.com> From: Auger Eric Message-ID: <3741c034-08f1-9dbb-ab06-434f3a8bd782@redhat.com> Date: Wed, 20 Nov 2019 11:18:12 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: 5HWBhLnLMeGUl4cuPBFxxQ-1 X-Mimecast-Spam-Score: 0 Cc: "kevin.tian@intel.com" , "vincent.stehle@arm.com" , "ashok.raj@intel.com" , "marc.zyngier@arm.com" , "tina.zhang@intel.com" X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Tomasz, On 11/20/19 9:15 AM, Tomasz Nowicki wrote: > Hi Eric, > > On 11.07.2019 15:56, Eric Auger wrote: >> This series brings the VFIO part of HW nested paging support >> in the SMMUv3. >> >> The series depends on: >> [PATCH v9 00/14] SMMUv3 Nested Stage Setup (IOMMU part) >> (https://www.spinics.net/lists/kernel/msg3187714.html) >> >> 3 new IOCTLs are introduced that allow the userspace to >> 1) pass the guest stage 1 configuration >> 2) pass stage 1 MSI bindings >> 3) invalidate stage 1 related caches >> >> They map onto the related new IOMMU API functions. >> >> We introduce the capability to register specific interrupt >> indexes (see [1]). A new DMA_FAULT interrupt index allows to register >> an eventfd to be signaled whenever a stage 1 related fault >> is detected at physical level. Also a specific region allows >> to expose the fault records to the user space. >> >> Best Regards >> >> Eric >> >> This series can be found at: >> https://github.com/eauger/linux/tree/v5.3.0-rc0-2stage-v9 > > I think you have already tested on ThunderX2, but as a formality, for > the whole series: > > Tested-by: Tomasz Nowicki > qemu: https://github.com/eauger/qemu/tree/v4.1.0-rc0-2stage-rfcv5 > kernel: https://github.com/eauger/linux/tree/v5.3.0-rc0-2stage-v9 + > Shameer's fix patch > > In my test I assigned Intel 82574L NIC and perform iperf tests. Thank you for your testing efforts. > > Other folks from Marvell claimed this to be important feature so I asked > them to review and speak up on mailing list. That's nice to read that! So it is time for me to rebase both the iommu and vfio parts. I will submit something quickly. Then I would encourage the review efforts to focus first on the iommu part. Thanks Eric > > Thanks, > Tomasz > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm