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Tue, 11 Feb 2020 18:09:06 +0000 (UTC) Received: from [10.36.116.37] (ovpn-116-37.ams2.redhat.com [10.36.116.37]) by smtp.corp.redhat.com (Postfix) with ESMTPS id EB2A360499; Tue, 11 Feb 2020 18:09:01 +0000 (UTC) Subject: Re: [kvm-unit-tests PATCH v2 4/9] arm: pmu: Check Required Event Support To: Peter Maydell References: <20200130112510.15154-1-eric.auger@redhat.com> <20200130112510.15154-5-eric.auger@redhat.com> From: Auger Eric Message-ID: <45a29624-764f-acb2-dcc8-294bc591032e@redhat.com> Date: Tue, 11 Feb 2020 19:08:59 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Cc: kvm-devel , Marc Zyngier , QEMU Developers , qemu-arm , Andre Przywara , Andrew Murray , kvmarm@lists.cs.columbia.edu, Eric Auger X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Peter, On 2/11/20 4:33 PM, Peter Maydell wrote: > On Thu, 30 Jan 2020 at 11:25, Eric Auger wrote: >> >> If event counters are implemented check the common events >> required by the PMUv3 are implemented. >> >> Some are unconditionally required (SW_INCR, CPU_CYCLES, >> either INST_RETIRED or INST_SPEC). Some others only are >> required if the implementation implements some other features. >> >> Check those wich are unconditionally required. >> >> This test currently fails on TCG as neither INST_RETIRED >> or INST_SPEC are supported. >> >> Signed-off-by: Eric Auger >> >> --- >> > >> +static bool is_event_supported(uint32_t n, bool warn) >> +{ >> + uint64_t pmceid0 = read_sysreg(pmceid0_el0); >> + uint64_t pmceid1 = read_sysreg_s(PMCEID1_EL0); >> + bool supported; >> + uint64_t reg; >> + >> + /* >> + * The low 32-bits of PMCEID0/1 respectly describe > > "respectively" > >> + * event support for events 0-31/32-63. Their High >> + * 32-bits describe support for extended events >> + * starting at 0x4000, using the same split. >> + */ >> + if (n >= 0x0 && n <= 0x3F) >> + reg = (pmceid0 & 0xFFFFFFFF) | ((pmceid1 & 0xFFFFFFFF) << 32); >> + else if (n >= 0x4000 && n <= 0x403F) >> + reg = (pmceid0 >> 32) | ((pmceid1 >> 32) << 32); >> + else >> + abort(); >> + >> + supported = reg & (1UL << (n & 0x3F)); >> + >> + if (!supported && warn) >> + report_info("event %d is not supported", n); >> + return supported; >> +} >> + >> +static void test_event_introspection(void) >> +{ >> + bool required_events; >> + >> + if (!pmu.nb_implemented_counters) { >> + report_skip("No event counter, skip ..."); >> + return; >> + } >> + >> + /* PMUv3 requires an implementation includes some common events */ >> + required_events = is_event_supported(0x0, true) /* SW_INCR */ && >> + is_event_supported(0x11, true) /* CPU_CYCLES */ && >> + (is_event_supported(0x8, true) /* INST_RETIRED */ || >> + is_event_supported(0x1B, true) /* INST_PREC */); >> + >> + if (pmu.version == 0x4) { > > This condition will only test for v8.1-required events if the PMU > is exactly 8.1, so you lose coverage if the implementation happens > to support ARMv8.4-PMU. Hopefully you have already bailed out > for "ID_AA64DFR0_EL1.PMUVer == 0xf" which means "non-standard IMPDEF > PMU", in which case you can just check >= 0x4. OK thanks Eric > >> + /* ARMv8.1 PMU: STALL_FRONTEND and STALL_BACKEND are required */ >> + required_events = required_events && >> + is_event_supported(0x23, true) && >> + is_event_supported(0x24, true); >> + } >> + >> + report(required_events, "Check required events are implemented"); >> +} >> + >> #endif > > thanks > -- PMM > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm