From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3957CC2D0CF for ; Tue, 24 Dec 2019 15:48:56 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id C263C20643 for ; Tue, 24 Dec 2019 15:48:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C263C20643 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 3B79E4AEF9; Tue, 24 Dec 2019 10:48:55 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0msWSZEhZ8EX; Tue, 24 Dec 2019 10:48:54 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 093574AF5B; Tue, 24 Dec 2019 10:48:53 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 081004AF5E for ; Tue, 24 Dec 2019 10:48:40 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NuC82Hv1bHuv for ; Tue, 24 Dec 2019 10:48:38 -0500 (EST) Received: from inca-roads.misterjones.org (inca-roads.misterjones.org [213.251.177.50]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id B84E94AF1F for ; Tue, 24 Dec 2019 10:48:38 -0500 (EST) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=big-swifty.misterjones.org) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:AES256-GCM-SHA384:256) (Exim 4.80) (envelope-from ) id 1ijmQD-00050u-Uq; Tue, 24 Dec 2019 16:48:34 +0100 Date: Tue, 24 Dec 2019 15:48:33 +0000 Message-ID: <8636d9iv1q.wl-maz@kernel.org> From: Marc Zyngier To: Andrew Murray Subject: Re: [PATCH v2 08/18] arm64: KVM: add support to save/restore SPE profiling buffer controls In-Reply-To: <20191224151739.GP42593@e119886-lin.cambridge.arm.com> References: <20191220143025.33853-1-andrew.murray@arm.com> <20191220143025.33853-9-andrew.murray@arm.com> <20191221135755.70a6e8df@why> <20191224104929.GE42593@e119886-lin.cambridge.arm.com> <20191224151739.GP42593@e119886-lin.cambridge.arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: andrew.murray@arm.com, kvm@vger.kernel.org, catalin.marinas@arm.com, linux-kernel@vger.kernel.org, sudeep.holla@arm.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Sudeep Holla , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Tue, 24 Dec 2019 15:17:39 +0000, Andrew Murray wrote: > > On Tue, Dec 24, 2019 at 10:49:30AM +0000, Andrew Murray wrote: > > On Sat, Dec 21, 2019 at 01:57:55PM +0000, Marc Zyngier wrote: > > > On Fri, 20 Dec 2019 14:30:15 +0000 > > > Andrew Murray wrote: > > > > > > > From: Sudeep Holla > > > > > > > > Currently since we don't support profiling using SPE in the guests, > > > > we just save the PMSCR_EL1, flush the profiling buffers and disable > > > > sampling. However in order to support simultaneous sampling both in > > > > > > Is the sampling actually simultaneous? I don't believe so (the whole > > > series would be much simpler if it was). > > > > No the SPE is used by either the guest or host at any one time. I guess > > the term simultaneous was used to refer to illusion given to both guest > > and host that they are able to use it whenever they like. I'll update > > the commit message to drop the magic. > > > > > > > > > > > the host and guests, we need to save and reatore the complete SPE > > > > > > s/reatore/restore/ > > > > Noted. > > > > > > > > > > > profiling buffer controls' context. > > > > > > > > Let's add the support for the same and keep it disabled for now. > > > > We can enable it conditionally only if guests are allowed to use > > > > SPE. > > > > > > > > Signed-off-by: Sudeep Holla > > > > [ Clear PMBSR bit when saving state to prevent spurious interrupts ] > > > > Signed-off-by: Andrew Murray > > > > --- > > > > arch/arm64/kvm/hyp/debug-sr.c | 51 +++++++++++++++++++++++++++++------ > > > > 1 file changed, 43 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/arch/arm64/kvm/hyp/debug-sr.c b/arch/arm64/kvm/hyp/debug-sr.c > > > > index 8a70a493345e..12429b212a3a 100644 > > > > --- a/arch/arm64/kvm/hyp/debug-sr.c > > > > +++ b/arch/arm64/kvm/hyp/debug-sr.c > > > > @@ -85,7 +85,8 @@ > > > > default: write_debug(ptr[0], reg, 0); \ > > > > } > > > > > > > > -static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) > > > > +static void __hyp_text > > > > +__debug_save_spe_nvhe(struct kvm_cpu_context *ctxt, bool full_ctxt) > > > > > > nit: don't split lines like this if you can avoid it. You can put the > > > full_ctxt parameter on a separate line instead. > > > > Yes understood. > > > > > > > > > > > { > > > > u64 reg; > > > > > > > > @@ -102,22 +103,46 @@ static void __hyp_text __debug_save_spe_nvhe(struct kvm_cpu_context *ctxt) > > > > if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) > > > > return; > > > > > > > > - /* No; is the host actually using the thing? */ > > > > - reg = read_sysreg_s(SYS_PMBLIMITR_EL1); > > > > - if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) > > > > + /* Save the control register and disable data generation */ > > > > + ctxt->sys_regs[PMSCR_EL1] = read_sysreg_el1(SYS_PMSCR); > > > > + > > > > + if (!ctxt->sys_regs[PMSCR_EL1]) > > > > > > Shouldn't you check the enable bits instead of relying on the whole > > > thing being zero? > > > > Yes that would make more sense (E1SPE and E0SPE). > > > > I feel that this check makes an assumption about the guest/host SPE > > driver... What happens if the SPE driver writes to some SPE registers > > but doesn't enable PMSCR? If the guest is also using SPE then those > > writes will be lost, when the host returns and the SPE driver enables > > SPE it won't work. > > > > With a quick look at the SPE driver I'm not sure this will happen, but > > even so it makes me nervous relying on these assumptions. I wonder if > > this risk is present in other devices? As a rule of thumb, you should always save whatever you're about to overwrite if the registers are not under exclusive control of KVM. No exception. So if the guest is willing to use SPE *and* that it isn't enabled on the host, these registers have to be saved on vcpu_load() and restored on vcpu_put(). If SPE is enabled on the host, then trapping has to be enabled, and no tracing occurs in the guest for this time slice. > In fact, this may be a good reason to trap the SPE registers - this would > allow you to conditionally save/restore based on a dirty bit. It would > also allow you to re-evaluate the SPE interrupt (for example when the guest > clears the status register) and thus potentially reduce any black hole. I don't see what trapping buys you in the expected case (where the guest is tracing and the host isn't). To clear PMBSR_EL1.S, you first need to know that an interrupt has fired. So this brings you exactly nothing in this particular case, and just adds overhead for everything else. The whole point of the architecture is that in the non-contended case, we can give SPE to the guest and mostly forget about it. I strongly suggest that you start with the simplest possible, non broken implementation. It doesn't matter if the black holes last for seconds for now. Once you have something that looks reasonable, we can evaluate how to improve on it by throwing actual HW and workloads at it. M. -- Jazz is not dead, it just smells funny. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm