From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 117BACA9ED0 for ; Fri, 1 Nov 2019 15:13:46 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 9A4B621734 for ; Fri, 1 Nov 2019 15:13:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A4B621734 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E1E784ACF4; Fri, 1 Nov 2019 11:13:44 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id krrud5G0VKQZ; Fri, 1 Nov 2019 11:13:43 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id DCC9B4ACE8; Fri, 1 Nov 2019 11:13:43 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id A52A54ACB0 for ; Fri, 1 Nov 2019 11:13:42 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XIeGVmnKvzIB for ; Fri, 1 Nov 2019 11:13:41 -0400 (EDT) Received: from inca-roads.misterjones.org (inca-roads.misterjones.org [213.251.177.50]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id 810404ACE8 for ; Fri, 1 Nov 2019 11:13:41 -0400 (EDT) Received: from 138.105.71.37.rev.sfr.net ([37.71.105.138] helo=big-swifty.misterjones.org) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:AES256-GCM-SHA384:256) (Exim 4.80) (envelope-from ) id 1iQYcL-0008EX-Qz; Fri, 01 Nov 2019 16:13:37 +0100 Date: Fri, 01 Nov 2019 15:13:37 +0000 Message-ID: <86eeyry6hq.wl-maz@kernel.org> From: Marc Zyngier To: Zenghui Yu Subject: Re: [PATCH v2 09/36] irqchip/gic-v3: Add GICv4.1 VPEID size discovery In-Reply-To: References: <20191027144234.8395-1-maz@kernel.org> <20191027144234.8395-10-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 EasyPG/1.0.0 Emacs/26 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 37.71.105.138 X-SA-Exim-Rcpt-To: yuzenghui@huawei.com, kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, eric.auger@redhat.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, tglx@linutronix.de, jason@lakedaemon.net, lorenzo.pieralisi@arm.com, Andrew.Murray@arm.com, jnair@marvell.com, rrichter@marvell.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false Cc: Lorenzo Pieralisi , Jason Cooper , linux-kernel@vger.kernel.org, Robert Richter , Jayachandran C , Thomas Gleixner , kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Archived-At: List-Archive: On Thu, 31 Oct 2019 12:02:24 +0000, Zenghui Yu wrote: > > Hi Marc, > > On 2019/10/27 22:42, Marc Zyngier wrote: > > While GICv4.0 mandates 16 bit worth of VPEIDs, GICv4.1 allows smaller > > implementations to be built. Add the required glue to dynamically > > compute the limit. > > > > Signed-off-by: Marc Zyngier > > --- > > drivers/irqchip/irq-gic-v3-its.c | 11 ++++++++++- > > drivers/irqchip/irq-gic-v3.c | 3 +++ > > include/linux/irqchip/arm-gic-v3.h | 5 +++++ > > 3 files changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > > index 94c9c2e9f917..40912b3fb0e1 100644 > > --- a/drivers/irqchip/irq-gic-v3-its.c > > +++ b/drivers/irqchip/irq-gic-v3-its.c > > @@ -121,7 +121,16 @@ struct its_node { > > #define ITS_ITT_ALIGN SZ_256 > > /* The maximum number of VPEID bits supported by VLPI commands > > */ > > -#define ITS_MAX_VPEID_BITS (16) > > +#define ITS_MAX_VPEID_BITS \ > > + ({ \ > > + int nvpeid = 16; \ > > + if (gic_rdists->has_rvpeid && \ > > + gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \ > > + nvpeid = 1 + (gic_rdists->gicd_typer2 & \ > > + GICD_TYPER2_VID); \ > > Does it make sense to let nvpeid not more than 16 here? As the spec says > "Values above 0x0F are RESERVED". But I don't know why should we have > this restriction ;-) This is something that Andrew raised in the previous version. My take on this is that properly implemented HW should give us something that matches the spec (in the 0-15 range), and I don't think that guarding against that is useful at this stage. My understanding is that once the architecture allows using the 16-31 range, we'll either use it directly because it is just a natural extension to the existing range, or they mean something different altogether and we'll get a new discovery bit somewhere. > Either way, > > Reviewed-by: Zenghui Yu Thanks, M. -- Jazz is not dead, it just smells funny. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm