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To: Andrew Jones Cc: Marc Zyngier , xu910121@sina.com, Dave Martin , kvmarm , qemu-devel X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu On Mon, 19 Oct 2020 at 14:40, Andrew Jones wrote: > > On Mon, Oct 19, 2020 at 12:43:33PM +0100, Peter Maydell wrote: > > Well, ID regs are special in the architecture -- they always exist > > and must RAZ/WI, even if they're not actually given any fields yet. > > This is different from other "unused" parts of the system register > > encoding space, which UNDEF. > > Table D12-2 confirms the register should be RAZ, as it says the register > is "RO, but RAZ if SVE is not implemented". Does "RO" imply "WI", though? > For the guest we inject an exception on writes, and for userspace we > require the value to be preserved on write. Sorry, I mis-spoke. They're RAZ, but not WI, just RO (which is to say they'll UNDEF if you try to write to them). > I think we should follow the spec, even for userspace access, and be RAZ > for when the feature isn't implemented. As for writes, assuming the > exception injection is what we want for the guest (not WI), then that's > correct. For userspace, I think we should continue forcing preservation > (which will force preservation of zero when it's RAZ). Yes, that sounds right. thanks -- PMM _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm