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Sat, 29 Jun 2019 21:29:58 -0700 (PDT) MIME-Version: 1.0 References: <20190321163623.20219-1-julien.grall@arm.com> <20190321163623.20219-12-julien.grall@arm.com> <0dfe120b-066a-2ac8-13bc-3f5a29e2caa3@arm.com> <20190621141606.GF18954@arrakis.emea.arm.com> <20190624153820.GH29120@arrakis.emea.arm.com> In-Reply-To: <20190624153820.GH29120@arrakis.emea.arm.com> From: Guo Ren Date: Sun, 30 Jun 2019 12:29:46 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file To: Catalin Marinas Cc: aou@eecs.berkeley.edu, Marc Zyngier , Anup Patel , Will Deacon , linux-kernel@vger.kernel.org, rppt@linux.ibm.com, hch@infradead.org, Atish Patra , Julien Grall , Palmer Dabbelt , gary@garyguo.net, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Archived-At: List-Archive: Hi Marinas, Thx for the reply On Mon, Jun 24, 2019 at 11:38 PM Catalin Marinas wrote: > > On Mon, Jun 24, 2019 at 12:35:35AM +0800, Guo Ren wrote: > > On Fri, Jun 21, 2019 at 10:16 PM Catalin Marinas > > wrote: > > > BTW, if you find the algorithm fairly straightforward ;), see this > > > bug-fix which took a formal model to identify: a8ffaaa060b8 ("arm64: > > > asid: Do not replace active_asids if already 0"). > [...] > > Btw, Is this detected by arm's aisd allocator TLA+ model ? Or a real > > bug report ? > > This specific bug was found by the TLA+ model checker (at the time we > were actually tracking down another bug with multi-threaded CPU sharing > the TLB, bug also confirmed by the formal model). Could you tell me the ref-link about "another bug with multi-threaded CPU sharing the TLB" ? In my concept, the multi-core asid mechanism is also applicable to multi-thread shared TLB, but it will generate redundant tlbflush. From the software design logic, multi-threaded is treated as multi-cores without error, but performance is not optimized. So in my RFC PATCH: [1], I try to reduce multi-threads' tlbflush in one CPU core with the fixed cpu ID bitmap hypothesis. 1: https://lore.kernel.org/linux-csky/CAJF2gTQ0xQtQY1t-g9FgWaxfDXppMkFooCQzTFy7+ouwUfyA6w@mail.gmail.com/T/#m2ed464d2dfb45ac6f5547fb3936adf2da456cb65 -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm