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From: Rob Herring <robh@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	Will Deacon <will@kernel.org>,
	kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v3 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
Date: Fri, 31 Jul 2020 17:21:31 -0600
Message-ID: <CAL_JsqLrHgtMmv=N-DwJR_1LDVXdu-5=A1-LMAOUbzpcuCa8cA@mail.gmail.com> (raw)
In-Reply-To: <20200729163800.GA24572@gaia>

On Wed, Jul 29, 2020 at 10:38 AM Catalin Marinas
<catalin.marinas@arm.com> wrote:
>
> On Fri, Jul 17, 2020 at 02:52:33PM -0600, Rob Herring wrote:
> > diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_hyp.h
> > index ce3080834bfa..ce5b0d9b12bf 100644
> > --- a/arch/arm64/include/asm/kvm_hyp.h
> > +++ b/arch/arm64/include/asm/kvm_hyp.h
> > @@ -46,6 +46,17 @@
> >  #define read_sysreg_el2(r)   read_sysreg_elx(r, _EL2, _EL1)
> >  #define write_sysreg_el2(v,r)        write_sysreg_elx(v, r, _EL2, _EL1)
> >
> > +static inline u64 __hyp_text read_sysreg_par(void)
> > +{
> > +     u64 par;
> > +     if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > +             dmb(sy);
> > +     par = read_sysreg(par_el1);
> > +     if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > +             dmb(sy);
> > +     return par;
> > +}
>
> Even if that's not always called on a critical path, I agree with Andrew
> that we could use alternatives here for dmb(sy).

His suggestion in the KVM code was to use cpus_have_final_cap() rather
than cpus_have_const_cap. But given it's just a dmb or nop,
alternatives is a better choice for all of these?

> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index baf5ce9225ce..3f798e0f1419 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -94,10 +94,16 @@ static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
> >       case TPIDR_EL1:         *val = read_sysreg_s(SYS_TPIDR_EL1);    break;
> >       case AMAIR_EL1:         *val = read_sysreg_s(SYS_AMAIR_EL12);   break;
> >       case CNTKCTL_EL1:       *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
> > -     case PAR_EL1:           *val = read_sysreg_s(SYS_PAR_EL1);      break;
> >       case DACR32_EL2:        *val = read_sysreg_s(SYS_DACR32_EL2);   break;
> >       case IFSR32_EL2:        *val = read_sysreg_s(SYS_IFSR32_EL2);   break;
> >       case DBGVCR32_EL2:      *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
> > +     case PAR_EL1:
> > +             if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > +                     dmb(sy);
> > +             *val = read_sysreg_s(SYS_PAR_EL1);
> > +             if (cpus_have_const_cap(ARM64_WORKAROUND_1508412))
> > +                     dmb(sy);
> > +             break;
> >       default:                return false;
> >       }
>
> Can't we use read_sysreg_par() directly here?

I assumed read_sysreg_s() was used here for some reason instead of
read_sysreg()?

> > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
> > index 8afb238ff335..98609532e61a 100644
> > --- a/arch/arm64/mm/fault.c
> > +++ b/arch/arm64/mm/fault.c
> > @@ -260,7 +260,17 @@ static bool __kprobes is_spurious_el1_translation_fault(unsigned long addr,
> >       local_irq_save(flags);
> >       asm volatile("at s1e1r, %0" :: "r" (addr));
> >       isb();
> > +     /*
> > +      * Arm Erratum 1508412 requires dmb(sy) before and after reads of
> > +      * PAR_EL1.
> > +      * As this location is not a hot path, just condition it on the config
> > +      * option.
> > +      */
> > +     if (IS_ENABLED(CONFIG_ARM64_ERRATUM_1508412))
> > +             dmb(sy);
> >       par = read_sysreg(par_el1);
> > +     if (IS_ENABLED(CONFIG_ARM64_ERRATUM_1508412))
> > +             dmb(sy);
> >       local_irq_restore(flags);
>
> Why not read_sysreg_par()?

Okay with read_sysreg_par() going in asm/sysreg.h instead? I was
hesitant to add it there as there didn't seem to be any other
instances of a function for a specific register there.

Rob
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      parent reply index

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17 20:52 [PATCH v3 0/3] Cortex-A77 erratum 1508412 workaround Rob Herring
2020-07-17 20:52 ` [PATCH v3 1/3] KVM: arm64: Print warning when cpu erratum can cause guests to deadlock Rob Herring
2020-07-17 20:52 ` [PATCH v3 2/3] arm64: Add part number for Arm Cortex-A77 Rob Herring
2020-07-17 20:52 ` [PATCH v3 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Rob Herring
2020-07-27 15:52   ` Andrew Scull
2020-07-29 16:38   ` Catalin Marinas
2020-07-30  8:22     ` Will Deacon
2020-07-31 22:55       ` Rob Herring
2020-08-03 15:03         ` Will Deacon
2020-07-31 23:21     ` Rob Herring [this message]

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