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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu > -----Original Message----- > From: linux-kernel-owner@vger.kernel.org owner@vger.kernel.org> On Behalf Of Palmer Dabbelt > Sent: Saturday, September 14, 2019 7:31 PM > To: will@kernel.org > Cc: guoren@kernel.org; Will Deacon ; > julien.thierry@arm.com; aou@eecs.berkeley.edu; james.morse@arm.com; > Arnd Bergmann ; suzuki.poulose@arm.com; > marc.zyngier@arm.com; catalin.marinas@arm.com; Anup Patel > ; linux-kernel@vger.kernel.org; > rppt@linux.ibm.com; Christoph Hellwig ; Atish Patra > ; julien.grall@arm.com; gary@garyguo.net; Paul > Walmsley ; christoffer.dall@arm.com; linux- > riscv@lists.infradead.org; kvmarm@lists.cs.columbia.edu; linux-arm- > kernel@lists.infradead.org; iommu@lists.linux-foundation.org > Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a > separate file > > On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@kernel.org wrote: > > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: > >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon wrote: > >> > > I'll keep my system use the same ASID for SMP + IOMMU :P > >> > > >> > You will want a separate allocator for that: > >> > > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.bruck > >> > er@arm.com > >> > >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or > >> different system, because it's difficult to synchronize the IO_ASID > >> when the CPU ASID is rollover. > >> But we could still use hardware broadcast TLB invalidation > >> instruction to uniformly manage the ASID and IO_ASID, or OTHER_ASID in > our IOMMU. > > > > That's probably a bad idea, because you'll likely stall execution on > > the CPU until the IOTLB has completed invalidation. In the case of > > ATS, I think an endpoint ATC is permitted to take over a minute to > > respond. In reality, I suspect the worst you'll ever see would be in > > the msec range, but that's still an unacceptable period of time to hold a > CPU. > > > >> Welcome to join our disscusion: > >> "Introduce an implementation of IOMMU in linux-riscv" > >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC > > > > I attended this session, but it unfortunately raised many more > > questions than it answered. > > Ya, we're a long way from figuring this out. For everyone's reference, here is our first attempt at RISC-V ASID allocator: http://archive.lwn.net:8080/linux-kernel/20190329045111.14040-1-anup.patel@wdc.com/T/#u Regards, Anup _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm