From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 559F7C34026 for ; Tue, 18 Feb 2020 17:43:58 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 1A9BC2464E for ; Tue, 18 Feb 2020 17:43:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1A9BC2464E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C9FE24AF17; Tue, 18 Feb 2020 12:43:56 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cFSn6STSL1UL; Tue, 18 Feb 2020 12:43:55 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C83474AF18; Tue, 18 Feb 2020 12:43:55 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id B39374AEE0 for ; Tue, 18 Feb 2020 12:43:54 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9QM6Hia-JTLY for ; Tue, 18 Feb 2020 12:43:53 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 91AAD4AF0F for ; Tue, 18 Feb 2020 12:43:53 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 09773FEC; Tue, 18 Feb 2020 09:43:53 -0800 (PST) Received: from [10.1.196.105] (eglon.cambridge.arm.com [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 24E873F703; Tue, 18 Feb 2020 09:43:52 -0800 (PST) Subject: Re: [PATCH 3/5] kvm: arm64: Limit PMU version to ARMv8.1 To: Marc Zyngier References: <20200216185324.32596-1-maz@kernel.org> <20200216185324.32596-4-maz@kernel.org> From: James Morse Message-ID: Date: Tue, 18 Feb 2020 17:43:51 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200216185324.32596-4-maz@kernel.org> Content-Language: en-GB Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, On 16/02/2020 18:53, Marc Zyngier wrote: > Our PMU code is only implementing the ARMv8.1 features, so let's > stick to this when reporting the feature set to the guest. > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 682fedd7700f..06b2d0dc6c73 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1093,6 +1093,11 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, > FEATURE(ID_AA64ISAR1_GPA) | > FEATURE(ID_AA64ISAR1_GPI)); > break; > + case SYS_ID_AA64DFR0_EL1: > + /* Limit PMU to ARMv8.1 */ Not just limit, but upgrade too! (force?) This looks safe because ARMV8_PMU_EVTYPE_EVENT always includes the extra bits this added, and the register is always trapped. The PMU version is also readable via ID_DFR0_EL1.PerfMon, should that be sanitised to be the same? (I don't think we've hidden an aarch64 feature that also existed in aarch32 before). Regardless: Reviewed-by: James Morse Thanks, James > + val &= ~FEATURE(ID_AA64DFR0_PMUVER); > + val |= FIELD_PREP(FEATURE(ID_AA64DFR0_PMUVER), 4); > + break; > } > > return val; > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm