From: Eric Auger <eauger@redhat.com>
To: Miguel Luis <miguel.luis@oracle.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev
Subject: Re: [PATCH v2 1/2] arm64: Add missing _EL12 encodings
Date: Thu, 28 Sep 2023 11:39:24 +0200 [thread overview]
Message-ID: <ec8ffc8f-1f53-61ca-8268-f13616a658d7@redhat.com> (raw)
In-Reply-To: <20230925162057.27548-2-miguel.luis@oracle.com>
Hi Miguel,
On 9/25/23 18:20, Miguel Luis wrote:
> Some _EL12 encodings are missing. Add them.
>
> Signed-off-by: Miguel Luis <miguel.luis@oracle.com>
> ---
> arch/arm64/include/asm/sysreg.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 38296579a4fd..6e167bbf44ff 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -568,18 +568,29 @@
>
> /* VHE encodings for architectural EL0/1 system registers */
> #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
> +#define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
> +#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
> +#define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
> +#define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
> +#define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
> #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
> #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
> #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
> +#define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
> #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
> #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
> #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
> #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
> #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
> #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
> +#define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
> +#define SYS_BRBCR_EL12 sys_reg(3, 5, 9, 0, 0)
isn't it sys_reg(2, 5, 9, 0, 0)?
> +#define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
> #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
> #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
> #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
> +#define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
> +#define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
> #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
> #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
> #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric
next prev parent reply other threads:[~2023-09-28 9:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 16:20 [PATCH v2 0/2] Fine grain sysregs allowed to trap for nested virtualization Miguel Luis
2023-09-25 16:20 ` [PATCH v2 1/2] arm64: Add missing _EL12 encodings Miguel Luis
2023-09-28 9:39 ` Eric Auger [this message]
2023-09-28 9:59 ` Miguel Luis
2023-09-25 16:20 ` [PATCH v2 2/2] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization Miguel Luis
2023-09-29 15:08 ` Eric Auger
2023-10-02 13:36 ` Miguel Luis
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