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Wed, 25 Mar 2020 11:28:03 +0000 MIME-Version: 1.0 Date: Wed, 25 Mar 2020 11:28:03 +0000 From: Marc Zyngier To: Zhenyu Ye Subject: Re: [PATCH v2 67/94] arm64: Add level-hinted TLB invalidation helper In-Reply-To: References: <20200211174938.27809-1-maz@kernel.org> <20200211174938.27809-68-maz@kernel.org> Message-ID: X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: yezhenyu2@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, suzuki.poulose@arm.com, andre.przywara@arm.com, christoffer.dall@arm.com, Dave.Martin@arm.com, james.morse@arm.com, alexandru.elisei@arm.com, jintack@cs.columbia.edu, julien.thierry.kdev@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Cc: kvm@vger.kernel.org, Andre Przywara , Dave Martin , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Zhenyu, On 2020-03-25 10:38, Zhenyu Ye wrote: > Hi Marc, > > On 2020/2/12 1:49, Marc Zyngier wrote: >> Add a level-hinted TLB invalidation helper that only gets used if >> ARMv8.4-TTL gets detected. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/include/asm/tlbflush.h | 30 ++++++++++++++++++++++++++++++ >> 1 file changed, 30 insertions(+) >> >> diff --git a/arch/arm64/include/asm/tlbflush.h >> b/arch/arm64/include/asm/tlbflush.h >> index bc3949064725..a3f70778a325 100644 >> --- a/arch/arm64/include/asm/tlbflush.h >> +++ b/arch/arm64/include/asm/tlbflush.h >> @@ -10,6 +10,7 @@ >> >> #ifndef __ASSEMBLY__ >> >> +#include >> #include >> #include >> #include >> @@ -59,6 +60,35 @@ >> __ta; \ >> }) >> >> +#define TLBI_TTL_MASK GENMASK_ULL(47, 44) >> + >> +#define __tlbi_level(op, addr, level) \ >> + do { \ >> + u64 arg = addr; \ >> + \ >> + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ >> + level) { \ >> + u64 ttl = level; \ >> + \ >> + switch (PAGE_SIZE) { \ >> + case SZ_4K: \ >> + ttl |= 1 << 2; \ >> + break; \ >> + case SZ_16K: \ >> + ttl |= 2 << 2; \ >> + break; \ >> + case SZ_64K: \ >> + ttl |= 3 << 2; \ >> + break; \ >> + } \ > > Can we define a macro here to replace the switch? It will be more > clearly and efficient. Such as: > > #define __TG ((PAGE_SHIFT - 12) / 2 + 1) > ttl |= __TG << 2; Let me rephrase this: a convoluted formula with magic numbers in it is clearer than the values documented in the specification (Table D5-53)? I have the exact opposite view. As for efficency, you do realize that the compiler always discards two third of this code on any possible configuration, right? I think the code above is the clearest way to express table D5-53, and the only missing bit is a reference to that table. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm