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[203.116.164.13]) by smtp.gmail.com with ESMTPSA id u17sm6671227pgf.8.2019.09.14.07.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Sep 2019 07:01:29 -0700 (PDT) Date: Sat, 14 Sep 2019 07:01:29 -0700 (PDT) X-Google-Original-Date: Sat, 14 Sep 2019 07:00:16 PDT (-0700) Subject: Re: [PATCH RFC 11/14] arm64: Move the ASID allocator code in a separate file In-Reply-To: <20190912140256.fwbutgmadpjbjnab@willie-the-truck> From: Palmer Dabbelt To: will@kernel.org Message-ID: Mime-Version: 1.0 (MHng) Cc: catalin.marinas@arm.com, Will Deacon , Atish Patra , julien.grall@arm.com, guoren@kernel.org, gary@garyguo.net, linux-riscv@lists.infradead.org, kvmarm@lists.cs.columbia.edu, rppt@linux.ibm.com, Christoph Hellwig , aou@eecs.berkeley.edu, Arnd Bergmann , marc.zyngier@arm.com, Paul Walmsley , linux-arm-kernel@lists.infradead.org, Anup Patel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Archived-At: List-Archive: On Thu, 12 Sep 2019 07:02:56 PDT (-0700), will@kernel.org wrote: > On Sun, Sep 08, 2019 at 07:52:55AM +0800, Guo Ren wrote: >> On Mon, Jun 24, 2019 at 6:40 PM Will Deacon wrote: >> > > I'll keep my system use the same ASID for SMP + IOMMU :P >> > >> > You will want a separate allocator for that: >> > >> > https://lkml.kernel.org/r/20190610184714.6786-2-jean-philippe.brucker@arm.com >> >> Yes, it is hard to maintain ASID between IOMMU and CPUMMU or different >> system, because it's difficult to synchronize the IO_ASID when the CPU >> ASID is rollover. >> But we could still use hardware broadcast TLB invalidation instruction >> to uniformly manage the ASID and IO_ASID, or OTHER_ASID in our IOMMU. > > That's probably a bad idea, because you'll likely stall execution on the > CPU until the IOTLB has completed invalidation. In the case of ATS, I think > an endpoint ATC is permitted to take over a minute to respond. In reality, I > suspect the worst you'll ever see would be in the msec range, but that's > still an unacceptable period of time to hold a CPU. > >> Welcome to join our disscusion: >> "Introduce an implementation of IOMMU in linux-riscv" >> 9 Sep 2019, 10:45 Jade-room-I&II (Corinthia Hotel Lisbon) RISC-V MC > > I attended this session, but it unfortunately raised many more questions > than it answered. Ya, we're a long way from figuring this out. _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm