From mboxrd@z Thu Jan 1 00:00:00 1970 From: Manivannan Sadhasivam Subject: Re: [PATCH 2/2] gpio: sch: Add interrupt support Date: Fri, 26 Apr 2019 23:16:45 +0530 Message-ID: <20190426174645.GB31161@Mani-XPS-13-9360> References: <1200464b-f969-ebc2-ae82-1f8ca98aaca1@siemens.com> <20190424103306.GC2654@lahna.fi.intel.com> <9377620b-d74a-04d9-a51e-8590400b1c0f@siemens.com> <20190426130615.GT9224@smile.fi.intel.com> <2f3da791-4a10-c2c4-dc5a-22ad16ed7be6@siemens.com> <20190426173329.GA31161@Mani-XPS-13-9360> <534a4812-e6d3-9b16-5142-ab214da3d661@siemens.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <534a4812-e6d3-9b16-5142-ab214da3d661@siemens.com> Sender: linux-kernel-owner@vger.kernel.org To: Jan Kiszka Cc: Andy Shevchenko , "Enrico Weigelt, metux IT consult" , Andy Shevchenko , Mika Westerberg , Linus Walleij , Bartosz Golaszewski , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , ACPI Devel Maling List , "Rafael J. Wysocki" List-Id: linux-acpi@vger.kernel.org On Fri, Apr 26, 2019 at 07:39:56PM +0200, Jan Kiszka wrote: > On 26.04.19 19:33, Manivannan Sadhasivam wrote: > > On Fri, Apr 26, 2019 at 08:20:19PM +0300, Andy Shevchenko wrote: > > > On Fri, Apr 26, 2019 at 7:05 PM Jan Kiszka wrote: > > > > > > > > On 26.04.19 16:42, Enrico Weigelt, metux IT consult wrote: > > > > > On 26.04.19 15:36, Jan Kiszka wrote: > > > > > > > > > > > At the same time, there are no real alternatives - to my> knowledge - for the value it brings (various bindings) to simply > > > > > switch> the engine. > > > > > Which value exactly does that collection of crude wrappers and broken > > > > > attempts to buypass the kernel (driving gpios via /dev/mem *facepalm*) > > > > > provide ? > > > > > > > > Leaving that blunt hack aside: > > > > > > > > import mraa > > > > > > > > pin = mraa.Gpio(13) > > > > pin.dir(mraa.DIR_OUT) > > > > pin.write(1) > > > > > > > > And the same goes for nodejs, java and c++. > > > > > > > > Moreover, this allows you to abstract away where "Pin 13" actually came from on > > > > that board if the kernel changes (BSP -> upstream...) or the extension board or > > > > ... > > > > > > The problem here is opaque number. This has to be chip + *relative* pin number/ > > > See this: > > > https://stackoverflow.com/questions/55532410/how-do-linux-gpio-numbers-get-their-values/55579640#55579640 > > > > > > > But for platform like 96Boards we don't need controller specific lookup, these > > are all handled by the platform code [1] so that the users can use the standard > > pinout number to access GPIOs. For instance, pin 23 on the Low Speed expansion > > header is the GPIO for all 96Boards platform, so the user can access that pin > > using 23 itself in the application and it will run across all supported > > 96Boards. > > Can you ensure stable numbering when probing order changes, e.g. due to > adding an extension board? > Good point! For tackling this, I'm planning to introduce an API for accessing the GPIO by its line name. It will be tricky to implement but once done, it will serve. Regards, Mani > Jan > > > > > That's one of the reason why we prefer MRAA. > > > > Thanks, > > Mani > > > > [1] https://github.com/intel-iot-devkit/mraa/blob/master/src/arm/96boards.c#L75 > > > > > -- > > > With Best Regards, > > > Andy Shevchenko > > -- > Siemens AG, Corporate Technology, CT RDA IOT SES-DE > Corporate Competence Center Embedded Linux From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4C7CC43218 for ; Fri, 26 Apr 2019 17:47:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 84CDD21537 for ; Fri, 26 Apr 2019 17:47:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="saq2xo4y" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726181AbfDZRqz (ORCPT ); Fri, 26 Apr 2019 13:46:55 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:42415 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726083AbfDZRqy (ORCPT ); Fri, 26 Apr 2019 13:46:54 -0400 Received: by mail-pg1-f194.google.com with SMTP id p6so1947565pgh.9 for ; Fri, 26 Apr 2019 10:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=LG37QFwhXYZEYAua0BnCrURDS41kX/WKOIH1DK3ar6Y=; b=saq2xo4yo4tvxIgOaMXVKPJkCrOoDQ4AGWTIkle+IZCN90EVXHkdhqU1B1RQuBZ5aP JsBPCpe+QmsE0X+PAWPc6oIhQ16ic3WJsitEljNzLy/g9SgbNEtM2xk4ajkUKwScnGg+ 235COxs9JuHdU1RjloJJsODEE7a+X9Hq5YQQexGVxuOJAxyQomarAugW3MreE6G62MaT roYaPpjwZL9b8FPlHElP6DHM/aB/iKN4+Ss8t2n1KhMmEwVoMN3DI1Bo3Y5rjlb5+QKz zgdk9+Pd3G+MxLF1VdlDj6Ak5im9zpBFXyJB82sqWN0oqwnumteo6GzUosmE4mOL6JuB W+fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=LG37QFwhXYZEYAua0BnCrURDS41kX/WKOIH1DK3ar6Y=; b=Uwi9OzSbV9qXO5NQ+a6pTny7hQDz51tsCpuw0u5uiQd0K1hU+2Bpx+NH3VE7SzYHop pUxn6oCvf2cD+O/c7k0HweqNd212FTc4geszQD+1zrEzyz5LeoeKXXlyjQmJFMavbEpR lJPSmaXN7ub/T9BDdXRRsJyVIP5tYmUtPFfPl7X6uXQu8jlK/QPLLQCYlITCoAA21wG0 N0nlU+Xm8Dq8DuVOqgrLQjd6bg27+ZIkat2Yo67gJY7NbGzzTBHP93GpJUxzJ/96SkkM myxoWzrXbH4TUxIhiGv2KKieE2juJF5xek0u3ylSO630ifPEWglsCQlj4zkQYNFYX+Ij DNWQ== X-Gm-Message-State: APjAAAWXwtZo9y332dyDiiZQSn6RJEdzjobzFlA4rV09eBTrDk+tdunR s74NRbkWBLcmDxqrsjtsBk+8 X-Google-Smtp-Source: APXvYqy2VwuNbYHayVXPmNBL9JpV+tjzXn9WQNZiO8z1mDR+G6lJlYuFwGRrQtyROAR62zFvfIt0vw== X-Received: by 2002:a63:7e10:: with SMTP id z16mr46092563pgc.40.1556300813859; Fri, 26 Apr 2019 10:46:53 -0700 (PDT) Received: from Mani-XPS-13-9360 ([2405:204:72c4:4b94:e0ad:83b0:3987:aa05]) by smtp.gmail.com with ESMTPSA id 9sm14461629pgv.5.2019.04.26.10.46.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Apr 2019 10:46:53 -0700 (PDT) Date: Fri, 26 Apr 2019 23:16:45 +0530 From: Manivannan Sadhasivam To: Jan Kiszka Cc: Andy Shevchenko , "Enrico Weigelt, metux IT consult" , Andy Shevchenko , Mika Westerberg , Linus Walleij , Bartosz Golaszewski , Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , ACPI Devel Maling List , "Rafael J. Wysocki" Subject: Re: [PATCH 2/2] gpio: sch: Add interrupt support Message-ID: <20190426174645.GB31161@Mani-XPS-13-9360> References: <1200464b-f969-ebc2-ae82-1f8ca98aaca1@siemens.com> <20190424103306.GC2654@lahna.fi.intel.com> <9377620b-d74a-04d9-a51e-8590400b1c0f@siemens.com> <20190426130615.GT9224@smile.fi.intel.com> <2f3da791-4a10-c2c4-dc5a-22ad16ed7be6@siemens.com> <20190426173329.GA31161@Mani-XPS-13-9360> <534a4812-e6d3-9b16-5142-ab214da3d661@siemens.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline In-Reply-To: <534a4812-e6d3-9b16-5142-ab214da3d661@siemens.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Message-ID: <20190426174645.LdL744bobK3xM8IPZWN-AaHl4l8O12WzYT23zv9WyCw@z> On Fri, Apr 26, 2019 at 07:39:56PM +0200, Jan Kiszka wrote: > On 26.04.19 19:33, Manivannan Sadhasivam wrote: > > On Fri, Apr 26, 2019 at 08:20:19PM +0300, Andy Shevchenko wrote: > > > On Fri, Apr 26, 2019 at 7:05 PM Jan Kiszka wrote: > > > > > > > > On 26.04.19 16:42, Enrico Weigelt, metux IT consult wrote: > > > > > On 26.04.19 15:36, Jan Kiszka wrote: > > > > > > > > > > > At the same time, there are no real alternatives - to my> knowledge - for the value it brings (various bindings) to simply > > > > > switch> the engine. > > > > > Which value exactly does that collection of crude wrappers and broken > > > > > attempts to buypass the kernel (driving gpios via /dev/mem *facepalm*) > > > > > provide ? > > > > > > > > Leaving that blunt hack aside: > > > > > > > > import mraa > > > > > > > > pin = mraa.Gpio(13) > > > > pin.dir(mraa.DIR_OUT) > > > > pin.write(1) > > > > > > > > And the same goes for nodejs, java and c++. > > > > > > > > Moreover, this allows you to abstract away where "Pin 13" actually came from on > > > > that board if the kernel changes (BSP -> upstream...) or the extension board or > > > > ... > > > > > > The problem here is opaque number. This has to be chip + *relative* pin number/ > > > See this: > > > https://stackoverflow.com/questions/55532410/how-do-linux-gpio-numbers-get-their-values/55579640#55579640 > > > > > > > But for platform like 96Boards we don't need controller specific lookup, these > > are all handled by the platform code [1] so that the users can use the standard > > pinout number to access GPIOs. For instance, pin 23 on the Low Speed expansion > > header is the GPIO for all 96Boards platform, so the user can access that pin > > using 23 itself in the application and it will run across all supported > > 96Boards. > > Can you ensure stable numbering when probing order changes, e.g. due to > adding an extension board? > Good point! For tackling this, I'm planning to introduce an API for accessing the GPIO by its line name. It will be tricky to implement but once done, it will serve. Regards, Mani > Jan > > > > > That's one of the reason why we prefer MRAA. > > > > Thanks, > > Mani > > > > [1] https://github.com/intel-iot-devkit/mraa/blob/master/src/arm/96boards.c#L75 > > > > > -- > > > With Best Regards, > > > Andy Shevchenko > > -- > Siemens AG, Corporate Technology, CT RDA IOT SES-DE > Corporate Competence Center Embedded Linux