From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4242CC04AB1 for ; Thu, 9 May 2019 10:36:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 185F720644 for ; Thu, 9 May 2019 10:36:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725892AbfEIKgF (ORCPT ); Thu, 9 May 2019 06:36:05 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:37518 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725869AbfEIKgF (ORCPT ); Thu, 9 May 2019 06:36:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7715DA78; Thu, 9 May 2019 03:36:04 -0700 (PDT) Received: from e107155-lin (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EBFAE3F238; Thu, 9 May 2019 03:36:01 -0700 (PDT) Date: Thu, 9 May 2019 11:35:59 +0100 From: Sudeep Holla To: Will Deacon Cc: Hanjun Guo , Jeremy Linton , linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, catalin.marinas@arm.com, rjw@rjwysocki.net, lenb@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, linuxarm@huawei.com, john.garry@huawei.com, Hongbo Yao , Alexander Shishkin , Sudeep Holla Subject: Re: [PATCH v3 0/5] arm64: SPE ACPI enablement Message-ID: <20190509103559.GB8239@e107155-lin> References: <20190503232407.37195-1-jeremy.linton@arm.com> <5eaa1607-4bf0-a320-e9cf-2d51eca912c6@huawei.com> <82032e5b-0cb5-e48f-ab51-ba5d5f9dceec@arm.com> <819de863-92ff-51c5-9c35-880db4f6a922@huawei.com> <20190508165149.GB21553@e107155-lin> <20190509092810.GC2667@brain-police> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190509092810.GC2667@brain-police> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Thu, May 09, 2019 at 10:28:11AM +0100, Will Deacon wrote: > On Wed, May 08, 2019 at 05:51:49PM +0100, Sudeep Holla wrote: > > On Wed, May 08, 2019 at 05:35:51PM +0800, Hanjun Guo wrote: > > > +Cc Alexander. > > > > > > On 2019/5/8 1:58, Jeremy Linton wrote: > > > > Hi, > > > > > > > > On 5/4/19 6:06 AM, Hanjun Guo wrote: > > > >> Hi Jeremy, Mark, > > > >> > > > >> On 2019/5/4 7:24, Jeremy Linton wrote: > > > >>> This patch series enables the Arm Statistical Profiling > > > >>> Extension (SPE) on ACPI platforms. > > > >>> > > > >>> This is possible because ACPI 6.3 uses a previously > > > >>> reserved field in the MADT to store the SPE interrupt > > > >>> number, similarly to how the normal PMU is described. > > > >>> If a consistent valid interrupt exists across all the > > > >>> cores in the system, a platform device is registered. > > > >>> That then triggers the SPE module, which runs as normal. > > > >>> > > > >>> We also add the ability to parse the PPTT for IDENTICAL > > > >>> cores. We then use this to sanity check the single SPE > > > >>> device we create. This creates a bit of a problem with > > > >>> respect to the specification though. The specification > > > >>> says that its legal for multiple tree's to exist in the > > > >>> PPTT. We handle this fine, but what happens in the > > > >>> case of multiple tree's is that the lack of a common > > > >>> node with IDENTICAL set forces us to assume that there > > > >>> are multiple non-IDENTICAL cores in the machine. > > > >> > > > >> Adding this patch set on top of latest mainline kernel, > > > >> and tested on D06 which has the SPE feature, in boot message > > > >> shows it was probed successfully: > > > >> > > > >> arm_spe_pmu arm,spe-v1: probed for CPUs 0-95 [max_record_sz 128, align 4, features 0x7] > > > >> > > > >> but when I test it with spe events such as > > > >> > > > >> perf record -c 1024 -e arm_spe_0/branch_filter=0/ -o spe ls > > > >> > > > >> it fails with: > > > >> failed to mmap with 12 (Cannot allocate memory), > > > >> > > > >> Confirmed that patch [0] is merged and other perf events are working > > > >> fine. > > > > > > > > Its pretty easy to get into the weeds with this driver, does it work with examples like: > > > > > > > > https://lkml.org/lkml/2018/1/14/122 > > > > > > No, not work at all. > > > > > > SPE works on 5.0, but not work after 5.1-rc1, bisected to this commit: > > > > > > 5768402fd9c6 perf/ring_buffer: Use high order allocations for AUX buffers optimistically > > > > > > > Indeed this patch breaks SPE. As mentioned in the patch, it uses high > > order allocations for AUX buffers and SPE PMU setup_aux explicitly > > fails with the warning "unexpected high-order page for auxbuf!" if > > it encounters one. > > > > I don't know the intention of that check in SPE. Will ? > > Since SPE uses virtual addressing, we don't really care about the underlying > page layout so there's no need to use higher-order allocations. I suppose we > could theoretically map them at the pmd level in some cases, but ignoring > them should also be harmless and I suspect you can delete the check. > Yes, I did a quick look to see if we can do that, but couldn't find a clue. Not sure if that's any optimisation, we can use order from page_private and set the values accordingly ? > Does the patch below fix the problem? > Yes it should help, I tried exactly the same thing yesterday and it does fix the issue. Regards, Sudeep