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From: Mika Westerberg <>
To: Bjorn Helgaas <>,
	"Rafael J. Wysocki" <>
Cc: Len Brown <>, Lukas Wunner <>,
	Keith Busch <>,
	Alex Williamson <>,
	Alexandru Gagniuc <>,
	Mika Westerberg <>,,
Subject: [PATCH v2 2/2] PCI: Do not poll for PME if the device is in D3cold
Date: Wed, 12 Jun 2019 13:57:39 +0300
Message-ID: <> (raw)
In-Reply-To: <>

PME polling does not take into account that a device that is directly
connected to the host bridge may go into D3cold as well. This leads to a
situation where the PME poll thread reads from a config space of a
device that is in D3cold and gets incorrect information because the
config space is not accessible.

Here is an example from Intel Ice Lake system where two PCIe root ports
are in D3cold (I've instrumented the kernel to log the PMCSR register

  [   62.971442] pcieport 0000:00:07.1: Check PME status, PMCSR=0xffff
  [   62.971504] pcieport 0000:00:07.0: Check PME status, PMCSR=0xffff

Since 0xffff is interpreted so that PME is pending, the root ports will
be runtime resumed. This repeats over and over again essentially
blocking all runtime power management.

Prevent this from happening by checking whether the device is in D3cold
before its PME status is read.

Fixes: 71a83bd727cc ("PCI/PM: add runtime PM support to PCIe port")
Signed-off-by: Mika Westerberg <>
Reviewed-by: Lukas Wunner <>
Reviewed-by: Rafael J. Wysocki <>
Cc: # v3.6+
 drivers/pci/pci.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 87a1f902fa8e..720da09d4d73 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -2060,6 +2060,13 @@ static void pci_pme_list_scan(struct work_struct *work)
 			if (bridge && bridge->current_state != PCI_D0)
+			/*
+			 * If the device is in D3cold it should not be
+			 * polled either.
+			 */
+			if (pme_dev->dev->current_state == PCI_D3cold)
+				continue;
 			pci_pme_wakeup(pme_dev->dev, NULL);
 		} else {

  parent reply index

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-12 10:57 [PATCH v2 0/2] PCI: Power management improvements Mika Westerberg
2019-06-12 10:57 ` [PATCH v2 1/2] PCI: Add missing link delays required by the PCIe spec Mika Westerberg
2019-06-12 10:57 ` Mika Westerberg [this message]
2019-06-17 10:43 ` [PATCH v2 0/2] PCI: Power management improvements Rafael J. Wysocki

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