From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9107EC433E3 for ; Wed, 8 Jul 2020 21:15:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70ACC206E9 for ; Wed, 8 Jul 2020 21:15:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="OPXWFEOJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726187AbgGHVPI (ORCPT ); Wed, 8 Jul 2020 17:15:08 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:41854 "EHLO us-smtp-1.mimecast.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726185AbgGHVPI (ORCPT ); Wed, 8 Jul 2020 17:15:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1594242906; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EMbMxst1oiHtTJmDDNK1CEbufosoaisjf4HJnYds+98=; b=OPXWFEOJFLyKtiP9HdpTe0MW8LDIBSUfdNJaJaPSrfrudNpwVW0oVIB8mo2id28qZO1Jsp z5ooTOTU8q25kxgGLk5+mViuENz2kWNVdncnjj8xZU1Ksew4tdho4GrWh1RA+/DMlWQhK0 IeDSXcRNhuWUSofTUoTAmQ4Mh/BF3H0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-272-BIAWZdZ4PqiHkMnQ8240cw-1; Wed, 08 Jul 2020 17:15:04 -0400 X-MC-Unique: BIAWZdZ4PqiHkMnQ8240cw-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3A957E91F; Wed, 8 Jul 2020 21:15:02 +0000 (UTC) Received: from x1.localdomain.com (ovpn-112-5.ams2.redhat.com [10.36.112.5]) by smtp.corp.redhat.com (Postfix) with ESMTP id AE3ED79248; Wed, 8 Jul 2020 21:14:59 +0000 (UTC) From: Hans de Goede To: Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , "Rafael J . Wysocki" , Len Brown Cc: Hans de Goede , linux-pwm@vger.kernel.org, intel-gfx , dri-devel@lists.freedesktop.org, Andy Shevchenko , Mika Westerberg , linux-acpi@vger.kernel.org Subject: [PATCH v4 09/16] pwm: crc: Fix period changes not having any effect Date: Wed, 8 Jul 2020 23:14:25 +0200 Message-Id: <20200708211432.28612-10-hdegoede@redhat.com> In-Reply-To: <20200708211432.28612-1-hdegoede@redhat.com> References: <20200708211432.28612-1-hdegoede@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register I strongly suspect that the BACKLIGHT_EN register at address 0x51 really controls a separate output-only GPIO which is connected to the LCD panels backlight-enable input. Like how the PANEL_EN register at address 0x52 controls an output-only GPIO which is earmarked for the LCD panel's enable pin. If this is correct then this GPIO should really be added to the gpio-crystalcove.c driver and the PWM driver should stop poking it. But I've been unable to come up with a definitive answer here, so I'm keeping this as is for now. As the comment in the old code already indicates we must disable the PWM before we can change the clock divider. But the crc_pwm_disable() and crc_pwm_enable() calls the old code make for this only change the BACKLIGHT_EN register; and the value of that register does not matter for changing the period / the divider. What does matter is that the PWM_OUTPUT_ENABLE bit must be cleared before a new value can be written. This commit modifies crc_pwm_config() to clear PWM_OUTPUT_ENABLE instead when changing the period, so that period changes actually work. Note this fix will cause a significant behavior change on some devices using the CRC PWM output to drive their backlight. Before the PWM would always run with the output frequency configured by the BIOS at boot, now the period time specified by the i915 driver will actually be honored. Signed-off-by: Hans de Goede --- drivers/pwm/pwm-crc.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 44ec7d5b63e1..81232da0c767 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -82,14 +82,11 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, if (pwm_get_period(pwm) != period_ns) { int clk_div = crc_pwm_calc_clk_div(period_ns); - /* changing the clk divisor, need to disable fisrt */ - crc_pwm_disable(c, pwm); + /* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */ + regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0); regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE); - - /* enable back */ - crc_pwm_enable(c, pwm); } /* change the pwm duty cycle */ -- 2.26.2