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Wysocki" , Len Brown , linux-pwm@vger.kernel.org, intel-gfx , dri-devel@lists.freedesktop.org, Andy Shevchenko , Mika Westerberg , linux-acpi@vger.kernel.org Subject: Re: [PATCH v8 07/17] pwm: lpss: Always update state and set update bit Message-ID: <20200831111334.GE1688464@ulmo> References: <20200830125753.230420-1-hdegoede@redhat.com> <20200830125753.230420-8-hdegoede@redhat.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="84ND8YJRMFlzkrP4" Content-Disposition: inline In-Reply-To: <20200830125753.230420-8-hdegoede@redhat.com> User-Agent: Mutt/1.14.6 (2020-07-11) Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org --84ND8YJRMFlzkrP4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Aug 30, 2020 at 02:57:43PM +0200, Hans de Goede wrote: > This commit removes a check where we would skip writing the ctrl register > and then setting the update bit in case the ctrl register already contains > the correct values. >=20 > In a perfect world skipping the update should be fine in these cases, but > on Cherry Trail devices the AML code in the GFX0 devices' PS0 and PS3 > methods messes with the PWM controller. >=20 > The "ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase" pat= ch > earlier in this series stops the GFX0._PS0 method from messing with the P= WM > controller and on the DSDT-s inspected sofar the _PS3 method only reads > from the PWM controller (and turns it off before we get a change to do so= ): >=20 > { > PWMB =3D PWMC /* \_SB_.PCI0.GFX0.PWMC */ > PSAT |=3D 0x03 > Local0 =3D PSAT /* \_SB_.PCI0.GFX0.PSAT */ > } >=20 > The PWM controller getting turning off before we do this ourselves is > a bit annoying but not really an issue. >=20 > The problem this patch fixes comes from a new variant of the GFX0._PS3 co= de > messing with the PWM controller found on the Acer One 10 S1003 (1): >=20 > { > PWMB =3D PWMC /* \_SB_.PCI0.GFX0.PWMC */ > PWMT =3D PWMC /* \_SB_.PCI0.GFX0.PWMC */ > PWMT &=3D 0xFF0000FF > PWMT |=3D 0xC0000000 > PWMC =3D PWMT /* \_SB_.PCI0.GFX0.PWMT */ > PWMT =3D PWMC /* \_SB_.PCI0.GFX0.PWMC */ > Sleep (0x64) > PWMB &=3D 0x3FFFFFFF > PWMC =3D PWMB /* \_SB_.PCI0.GFX0.PWMB */ > PSAT |=3D 0x03 > Local0 =3D PSAT /* \_SB_.PCI0.GFX0.PSAT */ > } >=20 > This "beautiful" piece of code clears the base-unit part of the ctrl-reg, > which effectively disables the controller, and it sets the update flag > to apply this change. Then after this it restores the original ctrl-reg > value, so we do not see it has mucked with the controller. >=20 > *But* it does not set the update flag when restoring the original value. > So the check to see if we can skip writing the ctrl register succeeds > but since the update flag was not set, the old base-unit value of 0 is > still in use and the PWM controller is effectively disabled. >=20 > IOW this PWM controller poking means that we cannot trust the base-unit / > on-time-div value we read back from the PWM controller since it may not > have been applied/committed. Thus we must always update the ctrl-register > and set the update bit. Doesn't this now make patch 6/17 obsolete? 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