From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: Dave Hansen <dave.hansen@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "Rafael J . Wysocki" <rjw@rjwysocki.net>,
"H . Peter Anvin" <hpa@zytor.com>,
Tony Luck <tony.luck@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Andi Kleen <ak@linux.intel.com>,
Kuppuswamy Sathyanarayanan <knsathya@kernel.org>,
linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH v2] x86: Skip WBINVD instruction for VM guest
Date: Sat, 4 Dec 2021 03:54:27 +0300 [thread overview]
Message-ID: <20211204005427.ccinxlwwab3jsuct@black.fi.intel.com> (raw)
In-Reply-To: <2519e6b6-4f74-e2f8-c428-0fceb0e16472@intel.com>
On Fri, Dec 03, 2021 at 04:20:34PM -0800, Dave Hansen wrote:
> On 12/3/21 3:49 PM, Kirill A. Shutemov wrote:
> > - ACPI_FLUSH_CPU_CACHE();
> > + if (acpi_state >= ACPI_STATE_S1 && acpi_state <= ACPI_STATE_S3)
> > + ACPI_FLUSH_CPU_CACHE();
>
> It's a bit of a bummer that this per-sleep-state logic has to be
> repeated so many time.
>
> If you pass acpi_state into ACPI_FLUSH_CPU_CACHE() can you centralize
> the set of places where that knowledge about which sleep states require
> flushing?
Yes, sure, it is doable. It we decide that it is the way to go.
> > TDX doesn't support these S- and C-states. TDX is only supports S0 and S5.
>
> This makes me a bit nervous. Is this "the first TDX implementation
> supports..." or "the TDX architecture *prohibits* supporting S1 (or
> whatever"?
TDX Virtual Firmware Design Guide only states that "ACPI S3 (not supported
by TDX guests)".
Kernel reports in dmesg "ACPI: PM: (supports S0 S5)".
But I don't see how any state beyond S0 and S5 make sense in TDX context.
Do you?
I find it neat that adjusting ACPI code to conform the spec makes TDX
work.
> I really think we need some kind of architecture guarantee. Without
> that, we risk breaking things if someone at our employer simply changes
> their mind.
Guarantees are hard.
If somebody change their mind we will get unexpected #VE and crash.
I think it is acceptable way to handle unexpected change in confidential
computing environment.
> The:
>
> > #define ACPI_FLUSH_CPU_CACHE_PHYS() \
> > if (!cpu_feature_enabled(XXX)) \
> > wbinvd(); \
>
> does seem simpler and less error-prone than this, though.
If it it the way to go, I can make a patch.
But there's no reason to have ACPI_FLUSH_CPU_CACHE_PHYS in addition to
ACPI_FLUSH_CPU_CACHE. All ACPI_FLUSH_CPU_CACHE can skip cache flush on
TDX.
--
Kirill A. Shutemov
next prev parent reply other threads:[~2021-12-04 0:54 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <YZPbQVwWOJCrAH78@zn.tnic>
2021-11-19 4:03 ` [PATCH v2] x86: Skip WBINVD instruction for VM guest Kuppuswamy Sathyanarayanan
2021-11-25 0:40 ` Thomas Gleixner
2021-12-02 22:21 ` Kirill A. Shutemov
2021-12-02 22:38 ` Dave Hansen
2021-12-02 23:48 ` Thomas Gleixner
2021-12-03 23:49 ` Kirill A. Shutemov
2021-12-04 0:20 ` Dave Hansen
2021-12-04 0:54 ` Kirill A. Shutemov [this message]
2021-12-06 15:35 ` Dave Hansen
2021-12-06 16:39 ` Dan Williams
2021-12-06 16:53 ` Dave Hansen
2021-12-06 17:51 ` Dan Williams
2021-12-04 20:27 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 0/4] ACPI/ACPICA: Only flush caches on S1/S2/S3 and C3 Kirill A. Shutemov
2021-12-06 12:29 ` [PATCH 1/4] ACPICA: Do not flush cache for on entering S4 and S5 Kirill A. Shutemov
2021-12-08 14:58 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 2/4] ACPI: PM: Remove redundant cache flushing Kirill A. Shutemov
2021-12-07 16:35 ` Rafael J. Wysocki
2021-12-09 13:32 ` Kirill A. Shutemov
2021-12-17 18:04 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 3/4] ACPI: processor idle: Only flush cache on entering C3 Kirill A. Shutemov
2021-12-06 15:03 ` Peter Zijlstra
2021-12-08 16:26 ` Rafael J. Wysocki
2021-12-09 13:33 ` Kirill A. Shutemov
2021-12-17 17:58 ` Rafael J. Wysocki
2021-12-06 12:29 ` [PATCH 4/4] ACPI: PM: Avoid cache flush on entering S4 Kirill A. Shutemov
2021-12-08 15:10 ` Rafael J. Wysocki
2021-12-08 16:04 ` Kirill A. Shutemov
2021-12-08 16:16 ` Rafael J. Wysocki
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