linux-acpi.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Steven Price <steven.price@arm.com>
To: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
	iommu@lists.linux-foundation.org
Cc: linuxarm@huawei.com, lorenzo.pieralisi@arm.com, joro@8bytes.org,
	robin.murphy@arm.com, wanghuiqiang@huawei.com,
	guohanjun@huawei.com, Sami.Mujawar@arm.com, jon@solid-run.com,
	eric.auger@redhat.com
Subject: Re: [PATCH v3 09/10] iommu/arm-smmu: Get associated RMR info and install bypass SMR
Date: Thu, 6 May 2021 16:17:15 +0100	[thread overview]
Message-ID: <501cd986-7f9c-9aa7-b4e9-f2ef98fb7a95@arm.com> (raw)
In-Reply-To: <20210420082751.1829-10-shameerali.kolothum.thodi@huawei.com>

On 20/04/2021 09:27, Shameer Kolothum wrote:
> From: Jon Nettleton <jon@solid-run.com>
> 
> Check if there is any RMR info associated with the devices behind
> the SMMU and if any, install bypass SMRs for them. This is to
> keep any ongoing traffic associated with these devices alive
> when we enable/reset SMMU during probe().
> 
> Signed-off-by: Jon Nettleton <jon@solid-run.com>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
>   drivers/iommu/arm/arm-smmu/arm-smmu.c | 42 +++++++++++++++++++++++++++
>   drivers/iommu/arm/arm-smmu/arm-smmu.h |  2 ++
>   2 files changed, 44 insertions(+)
> 
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index d8c6bfde6a61..4d2f91626d87 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> @@ -2102,6 +2102,43 @@ err_reset_platform_ops: __maybe_unused;
>   	return err;
>   }
>   
> +static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu)
> +{
> +	struct iommu_rmr *e;
> +	int i, cnt = 0;
> +	u32 smr;
> +
> +	for (i = 0; i < smmu->num_mapping_groups; i++) {
> +		smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
> +		if (!FIELD_GET(ARM_SMMU_SMR_VALID, smr))
> +			continue;
> +
> +		list_for_each_entry(e, &smmu->rmr_list, list) {
> +			if (FIELD_GET(ARM_SMMU_SMR_ID, smr) != e->sid)
> +				continue;
> +
> +			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
> +			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
> +			smmu->smrs[i].valid = true;
> +
> +			smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
> +			smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
> +			smmu->s2crs[i].cbndx = 0xff;
> +
> +			cnt++;
> +		}
> +	}

If I understand this correctly - this is looking at the current
(hardware) configuration of the SMMU and attempting to preserve any
bypass SMRs. However from what I can tell it suffers from the following
two problems:

  (a) Only the ID of the SMR is being checked, not the MASK. So if the
firmware has setup an SMR matching a number of streams this will break.

  (b) The SMMU might not be enabled at all (CLIENTPD==1) or bypass
enabled for unmatched streams (USFCFG==0).

Certainly in my test setup case (b) applies and so this doesn't work.
Perhaps something like the below would work better? (It works in the
case of the SMMU not enabled - I've not tested case (a)).

Steve

----8<----
static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu)
{
	struct iommu_rmr *e;
	int i, cnt = 0;
	u32 smr;
	u32 reg;

	reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0);

	if ((reg & ARM_SMMU_sCR0_USFCFG) && !(reg & ARM_SMMU_sCR0_CLIENTPD)) {
		/*
		 * SMMU is already enabled and disallowing bypass, so preserve
		 * the existing SMRs
		 */
		for (i = 0; i < smmu->num_mapping_groups; i++) {
			smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
			if (!FIELD_GET(ARM_SMMU_SMR_VALID, smr))
				continue;
			smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
			smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
			smmu->smrs[i].valid = true;
		}
	}

	list_for_each_entry(e, &smmu->rmr_list, list) {
		u32 sid = e->sid;

		i = arm_smmu_find_sme(smmu, sid, ~0);
		if (i < 0)
			continue;
		if (smmu->s2crs[i].count == 0) {
			smmu->smrs[i].id = sid;
			smmu->smrs[i].mask = ~0;
			smmu->smrs[i].valid = true;
		}
		smmu->s2crs[i].count++;
		smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
		smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
		smmu->s2crs[i].cbndx = 0xff;

		cnt++;
	}

	if ((reg & ARM_SMMU_sCR0_USFCFG) && !(reg & ARM_SMMU_sCR0_CLIENTPD)) {
		/* Remove the valid bit for unused SMRs */
		for (i = 0; i < smmu->num_mapping_groups; i++) {
			if (smmu->s2crs[i].count == 0)
				smmu->smrs[i].valid = false;
		}
	}

	dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt,
		   cnt == 1 ? "" : "s");
}

  reply	other threads:[~2021-05-06 15:17 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-20  8:27 [PATCH v3 00/10] ACPI/IORT: Support for IORT RMR node Shameer Kolothum
2021-04-20  8:27 ` [PATCH v3 01/10] ACPI/IORT: Add support for RMR node parsing Shameer Kolothum
2021-04-20  8:27 ` [PATCH v3 02/10] iommu/dma: Introduce generic helper to retrieve RMR info Shameer Kolothum
2021-04-20 12:04   ` kernel test robot
2021-04-20 12:32   ` kernel test robot
2021-04-20 12:59   ` kernel test robot
2021-04-20  8:27 ` [PATCH v3 03/10] ACPI/IORT: Add a helper to retrieve RMR memory regions Shameer Kolothum
2021-04-20  8:27 ` [PATCH v3 04/10] iommu/dma: Add a helper function to reserve RMRs for IOMMU drivers Shameer Kolothum
2021-04-20 12:07   ` kernel test robot
2021-04-20 13:32   ` kernel test robot
2021-04-20  8:27 ` [PATCH v3 05/10] iommu/arm-smmu-v3: Introduce strtab init helper Shameer Kolothum
2021-04-20  8:27 ` [PATCH v3 06/10] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent() Shameer Kolothum
2021-04-20  8:27 ` [PATCH v3 07/10] iommu/arm-smmu-v3: Get associated RMR info and install bypass STE Shameer Kolothum
2021-04-20  8:27 ` [PATCH v3 08/10] iommu/arm-smmu-v3: Reserve any RMR regions associated with a dev Shameer Kolothum
2021-05-07 10:01   ` Robin Murphy
2021-05-10  9:19     ` Shameerali Kolothum Thodi
2021-05-10 14:22       ` Robin Murphy
2021-04-20  8:27 ` [PATCH v3 09/10] iommu/arm-smmu: Get associated RMR info and install bypass SMR Shameer Kolothum
2021-05-06 15:17   ` Steven Price [this message]
2021-05-07  9:52     ` Robin Murphy
2021-05-10  8:40     ` Shameerali Kolothum Thodi
2021-05-10 11:51       ` Jon Nettleton
2021-04-20  8:27 ` [PATCH v3 10/10] iommu/arm-smmu: Reserve any RMR regions associated with a dev Shameer Kolothum
2021-04-20 14:18   ` kernel test robot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=501cd986-7f9c-9aa7-b4e9-f2ef98fb7a95@arm.com \
    --to=steven.price@arm.com \
    --cc=Sami.Mujawar@arm.com \
    --cc=eric.auger@redhat.com \
    --cc=guohanjun@huawei.com \
    --cc=iommu@lists.linux-foundation.org \
    --cc=jon@solid-run.com \
    --cc=joro@8bytes.org \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linuxarm@huawei.com \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=robin.murphy@arm.com \
    --cc=shameerali.kolothum.thodi@huawei.com \
    --cc=wanghuiqiang@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).