From: John Garry <john.garry@huawei.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: mika.westerberg@linux.intel.com, rafael@kernel.org,
rjw@rjwysocki.net, hanjun.guo@linaro.org, robh+dt@kernel.org,
bhelgaas@google.com, arnd@arndb.de, mark.rutland@arm.com,
olof@lixom.net, dann.frazier@canonical.com,
andy.shevchenko@gmail.com, robh@kernel.org, joe@perches.com,
benh@kernel.crashing.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
linuxarm@huawei.com, minyard@acm.org, devicetree@vger.kernel.org,
linux-arch@vger.kernel.org, rdunlap@infradead.org
Subject: Re: [PATCH v13 7/9] ACPI: Translate the I/O range of non-MMIO devices before scanning
Date: Wed, 14 Feb 2018 16:52:59 +0000 [thread overview]
Message-ID: <65185a4d-c712-4486-d713-3fa9de14e35d@huawei.com> (raw)
In-Reply-To: <20180214161635.GA13849@e107981-ln.cambridge.arm.com>
On 14/02/2018 16:16, Lorenzo Pieralisi wrote:
> On Wed, Feb 14, 2018 at 01:45:31AM +0800, John Garry wrote:
>> On some platforms (such as arm64-based hip06/hip07), access to legacy
>> ISA/LPC devices through access IO space is required, similar to x86
>> platforms. As the I/O for these devices are not memory mapped like
>> PCI/PCIE MMIO host bridges, they require special low-level device
>> operations through some host to generate IO accesses, i.e. a non-
>> transparent bridge.
>>
>> Through the logical PIO framework, hosts are able to register address
>> ranges in the logical PIO space for IO accesses. For hosts which require
>> a LLDD to generate the IO accesses, through the logical PIO framework
>> the host also registers accessors as a backend to generate the physical
>> bus transactions for IO space accesses (called indirect IO).
>>
>> When describing the indirect IO child device in APCI tables, the IO
>> resource is the host-specific address for the child (generally a
>> bus address).
>> An example is as follows:
>> Device (LPC0) {
>> Name (_HID, "HISI0191") // HiSi LPC
>> Name (_CRS, ResourceTemplate () {
>> Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
>> })
>> }
>>
>> Device (LPC0.IPMI) {
>> Name (_HID, "IPI0001")
>> Name (LORS, ResourceTemplate() {
>> QWordIO (
>> ResourceConsumer,
>> MinNotFixed, // _MIF
>> MaxNotFixed, // _MAF
>> PosDecode,
>> EntireRange,
>> 0x0, // _GRA
>> 0xe4, // _MIN
>> 0x3fff, // _MAX
>> 0x0, // _TRA
>> 0x04, // _LEN
>> , ,
>> BTIO
>> )
>> })
>>
>> Since the IO resource for the child is a host-specific address,
>> special translation are required to retrieve the logical PIO address
>> for that child.
>
Hi Lorenzo,
> The problem I have with this patchset and with pretending that the ACPI
> bits are generic is that the rules used to translate resources (I am
> referring to LPC0.IPMI above) are documented _nowhere_ which means that
> making this series generic code is just wishful thinking - there are no
> bindings backing it, it will never ever be used on a platform different
> from the one you are pushing this code for and I stated this already.
>
Right, it is working on the presumption that this is how all "indirectio
IO" hosts and children should/would be described in DSDT.
> Reworded differently - this is a Hisilicon driver it is not generic ACPI
> code; I can't see how it can be used on a multitude of platforms unless
> you specify FW level bindings.
>
>> To overcome the problem of associating this logical PIO address
>> with the child device, a scan handler is added to scan the ACPI
>> namespace for known indirect IO hosts. This scan handler creates an
>> MFD per child with the translated logical PIO address as it's IO
>> resource, as a substitute for the normal platform device which ACPI
>> would create during device enumeration.
>>
>> Signed-off-by: John Garry <john.garry@huawei.com>
>> Signed-off-by: Zhichang Yuan <yuanzhichang@hisilicon.com>
>> Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
>> ---
>> drivers/acpi/arm64/Makefile | 1 +
>> drivers/acpi/arm64/acpi_indirectio.c | 250 +++++++++++++++++++++++++++++++++++
>
> See above (and I do not understand what arm64 has to do with it).
Nothing apart from only being used by arm64 platforms today, which is
circumstantial.
>
> I understand you need to find a place to add the:
>
> acpi_indirect_io_scan_init()
>
> to be called from core ACPI code because ACPI can't handle probe
> dependencies in any other way but other than that this patch is
> a Hisilicon ACPI driver - there is nothing generic in it (or at
> least there are no standard bindings to make it so).
>
> Whether a callback from ACPI core code (acpi_scan_init()) to a driver
> specific hook is sane or not that's the question and the only reason
> why you want to add this in drivers/acpi/arm64 rather than, say,
> drivers/bus (as you do for the DT driver).
>
> I do not know Rafael's opinion on the above, I would like to help
> you make forward progress but please understand my concerns, mostly
> on FW side.
>
I did mention an alternative in my "ping" in v12 patch 7/9 (Feb 1), but
no response to this specific note so I kept on the same path.
Here's what I then wrote:
"I think another solution - which you may prefer - is to avoid adding
this scan handler (and all this other scan code) and add a check like
acpi_is_serial_bus_slave() [which checks the device parent versus a list
of known indirectIO hosts] to not enumerate these children, and do it
from the LLDD host probe instead (https://lkml.org/lkml/2017/6/16/250)"
Please consider this.
> Thanks,
> Lorenzo
>
>> drivers/acpi/internal.h | 5 +
>> drivers/acpi/scan.c | 1 +
>> 4 files changed, 257 insertions(+)
>> create mode 100644 drivers/acpi/arm64/acpi_indirectio.c
>>
Cheers,
John
next prev parent reply other threads:[~2018-02-14 16:52 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-13 17:45 [PATCH v13 0/9] LPC: legacy ISA I/O support John Garry
2018-02-13 17:45 ` [PATCH v13 1/9] LIB: Introduce a generic PIO mapping method John Garry
[not found] ` <1518543933-22456-2-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-02-13 23:05 ` dann frazier
2018-02-14 16:13 ` John Garry
2018-02-13 17:45 ` [PATCH v13 2/9] PCI: Remove unused __weak attribute in pci_register_io_range() John Garry
2018-02-13 17:45 ` [PATCH v13 3/9] PCI: Add fwnode handler as input param of pci_register_io_range() John Garry
2018-02-13 17:45 ` [PATCH v13 4/9] PCI: Apply the new generic I/O management on PCI IO hosts John Garry
2018-02-13 22:57 ` dann frazier
2018-02-14 15:42 ` John Garry
2018-02-14 16:05 ` dann frazier
2018-02-13 17:45 ` [PATCH v13 5/9] OF: Add missing I/O range exception for indirect-IO devices John Garry
[not found] ` <1518543933-22456-1-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-02-13 17:45 ` [PATCH v13 6/9] LPC: Support the LPC host on Hip06/Hip07 with DT bindings John Garry
2018-02-13 17:45 ` [PATCH v13 7/9] ACPI: Translate the I/O range of non-MMIO devices before scanning John Garry
2018-02-14 9:21 ` Rafael J. Wysocki
2018-02-14 12:48 ` John Garry
2018-02-14 13:53 ` Andy Shevchenko
2018-02-14 15:33 ` John Garry
2018-02-14 16:16 ` Andy Shevchenko
2018-02-15 17:07 ` John Garry
[not found] ` <59e5293f-0ea5-12f4-27db-b13bbcf0918b-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-02-16 14:42 ` Andy Shevchenko
[not found] ` <CAHp75VeTQg+A9o5Ox-k_9Qx8=JPEnqg1taVjcd8Zd2rfj_TMog-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-02-16 14:48 ` John Garry
2018-02-14 16:16 ` Lorenzo Pieralisi
2018-02-14 16:52 ` John Garry [this message]
2018-02-15 11:19 ` John Garry
2018-02-15 11:47 ` Rafael J. Wysocki
[not found] ` <CAJZ5v0jGvo+cutmvi3WSe1JNvQ1UvZhJr1mQ76=8=1E5Gq+iRg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-02-15 12:36 ` Lorenzo Pieralisi
2018-02-15 12:59 ` John Garry
2018-02-15 12:22 ` Andy Shevchenko
[not found] ` <CAHp75VfFKcnUVQwPUxynzp88RXWdV8VEqtXxd0=_Q_GJKO6UpQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-02-15 12:52 ` John Garry
[not found] ` <f7b3de31-46fb-f80e-511e-651fa815bddf-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
2018-02-15 12:55 ` Andy Shevchenko
2018-02-13 17:45 ` [PATCH v13 8/9] LPC, ACPI: Add the HISI LPC ACPI support John Garry
2018-02-13 17:45 ` [PATCH v13 9/9] MAINTAINERS: Add maintainer for HiSilicon LPC driver John Garry
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=65185a4d-c712-4486-d713-3fa9de14e35d@huawei.com \
--to=john.garry@huawei.com \
--cc=andy.shevchenko@gmail.com \
--cc=arnd@arndb.de \
--cc=benh@kernel.crashing.org \
--cc=bhelgaas@google.com \
--cc=dann.frazier@canonical.com \
--cc=devicetree@vger.kernel.org \
--cc=hanjun.guo@linaro.org \
--cc=joe@perches.com \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arch@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linuxarm@huawei.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=mika.westerberg@linux.intel.com \
--cc=minyard@acm.org \
--cc=olof@lixom.net \
--cc=rafael@kernel.org \
--cc=rdunlap@infradead.org \
--cc=rjw@rjwysocki.net \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).