From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DD0AC433E3 for ; Tue, 28 Jul 2020 11:17:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 77D782074F for ; Tue, 28 Jul 2020 11:17:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1595935056; bh=8cWIEcIxAMoEcv22ADKiBly1ykSpDfM0U+4sTr4DVUk=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=KNj/VdTuGHRpJcqm75pORXkv+jGU+Z78Nf5iTfAZ3Pcu1ZRc9rsXaspUc0VA7sMQ2 zEx2TIL0RqYEqAXtYj9alb8mtQfP14f1wwdTL9E0CizQlzuRgdVKUhP3+JJhgVE+rT PA1PFv6cvBZP9FFpRSJz8e2/IOkuU8TVzbomdFvE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728985AbgG1LRg (ORCPT ); Tue, 28 Jul 2020 07:17:36 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:35490 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728934AbgG1LRf (ORCPT ); Tue, 28 Jul 2020 07:17:35 -0400 Received: by mail-ot1-f68.google.com with SMTP id 93so4434479otx.2; Tue, 28 Jul 2020 04:17:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KnPUjAu22SOUCOm6g1IeFJhvhpLRbJ0m88Fl/eGEXik=; b=KvgW/E8Bzg1+rRhX/jTEV9Feu1A3rhdwSxBJus3+70/TvQ8PwSpN7L7SZrGBpvU6ar tjfTZNcAdjMmuitjkO+V52PuMaxCiNKGdp8/FaneARReHU5S++r3q8ddMYIsom+A+caE hy5ycunBwiXbnTO3La4lrd6dxjzjN77U3vM9SeZ8OxBbGiDHgI70L7y557e87sbW0EZ7 7JUINhzG5lsUOgVBV1ZW30egf8oHZQjTVGRAxvfq1T9rXRYm+Fl6LXzSoEVTQLX9CUwM tOMqGZZ34Tl3b0cFzMk7RM1v2osphAJXDT1f+fk+A4FWP7UMYMHqdWitkXo/bRJJCVAP gzOg== X-Gm-Message-State: AOAM530Nr/0mA/ZMPnt72omT4DtHHfuPXDHZ7+cXeZvEeTO8KkB6PDa9 voHbgiKqtm2DvEoJIsztd0kEf7kYXDBgGBAkgBQ= X-Google-Smtp-Source: ABdhPJwEafv59CVs5A2UJPEZNyJdT+8/NxOgu+3o+fqap2JowBj1l35GlCM4GXeZmBxNQU4lwA/8MSL1J5CW83FJF2c= X-Received: by 2002:a05:6830:1e5c:: with SMTP id e28mr5693951otj.118.1595935053275; Tue, 28 Jul 2020 04:17:33 -0700 (PDT) MIME-Version: 1.0 References: <20200720050500.23357-1-akshu.agrawal@amd.com> <20200720050500.23357-2-akshu.agrawal@amd.com> <27966cc7-cb5a-fd18-2244-5106d8853ea1@amd.com> In-Reply-To: <27966cc7-cb5a-fd18-2244-5106d8853ea1@amd.com> From: "Rafael J. Wysocki" Date: Tue, 28 Jul 2020 13:17:20 +0200 Message-ID: Subject: Re: [PATCH 1/4] ACPI: APD: Change name from ST to FCH To: "Agrawal, Akshu" Cc: "Rafael J. Wysocki" , Akshu Agrawal , Stephen Boyd , "Rafael J. Wysocki" , Len Brown , "open list:ACPI" , open list Content-Type: text/plain; charset="UTF-8" Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Tue, Jul 28, 2020 at 7:50 AM Agrawal, Akshu wrote: > > > On 7/27/2020 6:58 PM, Rafael J. Wysocki wrote: > > On Mon, Jul 20, 2020 at 7:06 AM Akshu Agrawal wrote: > >> AMD SoC general pupose clk is present in new platforms with > >> same MMIO mappings. We can reuse the same clk handler support > >> for other platforms. Hence, changing name from ST(SoC) to FCH(IP) > >> > >> Signed-off-by: Akshu Agrawal > > This patch and the [3/4] appear to be part of a larger series which > > isn't visible to me as a whole. > > Link to other patches: > > https://patchwork.kernel.org/patch/11672857/ > > https://patchwork.kernel.org/patch/11672861/ > > > > > Do you want me to apply them nevertheless? > > This patch on its own will cause compilation error as we need the second > patch. > > Since, there is dependency we need them to be merged together. Can you > or Stephen please suggest a way forward. I would prefer it to be routed through the clock tree. The APD changes are simple enough and I don't have any issues with them. Thanks! > >> --- > >> drivers/acpi/acpi_apd.c | 14 +++++++------- > >> .../linux/platform_data/{clk-st.h => clk-fch.h} | 10 +++++----- > >> 2 files changed, 12 insertions(+), 12 deletions(-) > >> rename include/linux/platform_data/{clk-st.h => clk-fch.h} (53%) > >> > >> diff --git a/drivers/acpi/acpi_apd.c b/drivers/acpi/acpi_apd.c > >> index ba2612e9a0eb..2d99e46add1a 100644 > >> --- a/drivers/acpi/acpi_apd.c > >> +++ b/drivers/acpi/acpi_apd.c > >> @@ -8,7 +8,7 @@ > >> */ > >> > >> #include > >> -#include > >> +#include > >> #include > >> #include > >> #include > >> @@ -79,11 +79,11 @@ static int misc_check_res(struct acpi_resource *ares, void *data) > >> return !acpi_dev_resource_memory(ares, &res); > >> } > >> > >> -static int st_misc_setup(struct apd_private_data *pdata) > >> +static int fch_misc_setup(struct apd_private_data *pdata) > >> { > >> struct acpi_device *adev = pdata->adev; > >> struct platform_device *clkdev; > >> - struct st_clk_data *clk_data; > >> + struct fch_clk_data *clk_data; > >> struct resource_entry *rentry; > >> struct list_head resource_list; > >> int ret; > >> @@ -106,7 +106,7 @@ static int st_misc_setup(struct apd_private_data *pdata) > >> > >> acpi_dev_free_resource_list(&resource_list); > >> > >> - clkdev = platform_device_register_data(&adev->dev, "clk-st", > >> + clkdev = platform_device_register_data(&adev->dev, "clk-fch", > >> PLATFORM_DEVID_NONE, clk_data, > >> sizeof(*clk_data)); > >> return PTR_ERR_OR_ZERO(clkdev); > >> @@ -135,8 +135,8 @@ static const struct apd_device_desc cz_uart_desc = { > >> .properties = uart_properties, > >> }; > >> > >> -static const struct apd_device_desc st_misc_desc = { > >> - .setup = st_misc_setup, > >> +static const struct apd_device_desc fch_misc_desc = { > >> + .setup = fch_misc_setup, > >> }; > >> #endif > >> > >> @@ -239,7 +239,7 @@ static const struct acpi_device_id acpi_apd_device_ids[] = { > >> { "AMD0020", APD_ADDR(cz_uart_desc) }, > >> { "AMDI0020", APD_ADDR(cz_uart_desc) }, > >> { "AMD0030", }, > >> - { "AMD0040", APD_ADDR(st_misc_desc)}, > >> + { "AMD0040", APD_ADDR(fch_misc_desc)}, > >> #endif > >> #ifdef CONFIG_ARM64 > >> { "APMC0D0F", APD_ADDR(xgene_i2c_desc) }, > >> diff --git a/include/linux/platform_data/clk-st.h b/include/linux/platform_data/clk-fch.h > >> similarity index 53% > >> rename from include/linux/platform_data/clk-st.h > >> rename to include/linux/platform_data/clk-fch.h > >> index 7cdb6a402b35..850ca776156d 100644 > >> --- a/include/linux/platform_data/clk-st.h > >> +++ b/include/linux/platform_data/clk-fch.h > >> @@ -1,17 +1,17 @@ > >> /* SPDX-License-Identifier: MIT */ > >> /* > >> - * clock framework for AMD Stoney based clock > >> + * clock framework for AMD misc clocks > >> * > >> * Copyright 2018 Advanced Micro Devices, Inc. > >> */ > >> > >> -#ifndef __CLK_ST_H > >> -#define __CLK_ST_H > >> +#ifndef __CLK_FCH_H > >> +#define __CLK_FCH_H > >> > >> #include > >> > >> -struct st_clk_data { > >> +struct fch_clk_data { > >> void __iomem *base; > >> }; > >> > >> -#endif /* __CLK_ST_H */ > >> +#endif /* __CLK_FCH_H */ > >> -- > >> 2.20.1 > >>