From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A71FC04AB6 for ; Tue, 28 May 2019 11:26:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2F6F12081C for ; Tue, 28 May 2019 11:26:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MoNcMVK+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726418AbfE1L0i (ORCPT ); Tue, 28 May 2019 07:26:38 -0400 Received: from mail-io1-f67.google.com ([209.85.166.67]:46573 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726400AbfE1L0i (ORCPT ); Tue, 28 May 2019 07:26:38 -0400 Received: by mail-io1-f67.google.com with SMTP id q21so15364466iog.13 for ; Tue, 28 May 2019 04:26:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=f63H1f5vJ9qAhu7DFKNxQrE7HwrSDOZLpyEalUp3FmA=; b=MoNcMVK+19rETeCSdS86WvUOF+QanmMuzgyz4USKjDCyqJy5ATxtytdNyWhLUhPzK7 3lLrA4eJp6EUT974Ua9jV0EW1h3qZbVDHKknvEVDD0yCnCqhV3q1+395Q30LTAn5kyK8 YJ/9sbJy+3/3jSrakrFSJGTunWBuqpSw9bTrYyQLBB2BB/1K8kUaCM1rOjXwFd8T1Kem x5hrYzZwsa+/3J4oY99XIA70l/itoCfN5VdEhdJgMf5CBuZH+xrGEZNyswxjs+4JDpGK x04m+SZ/gzISHQNxsntNIhWsx6Qp31qyqxvHeq1YNtXegLT6XWBd45+kOk48qErpubmi DSjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=f63H1f5vJ9qAhu7DFKNxQrE7HwrSDOZLpyEalUp3FmA=; b=s7fF7RPmxoM4gwfgBS6vQMFtimQuiQDVPS5EykYLC0k9qpWU/ECwpPPnqP1Uwlvdke KZv0WTBTcxJOF9cmUefwFPlqxEf2t83oT0QbAmpmq6kVM3Ngey3PC8lX/5Bsa8W//xJD BNMigQQ9F8yPKXKQE/LZBYrbEtPyGNk+o+nLGDwF06Xx5K8xL0M5H8kzD/43PUKwzsWJ RdyIAGdDOHrQcw9wXgAF24SOPlakD+0zu6X33Kg9KGTrQ1YK12YiZ+0GQNT3VjjdVNiU Fvs2clvAcQiffEZQX2RTqC4iZdKLIT+3hp79Nlf0ajnxcjgBfz/ZR8sx8xJYzp4UCO78 Abaw== X-Gm-Message-State: APjAAAU6EpB8fTlDSAgUvOyFZvj9UYRvERvA9fA9uryzpqU8PaJZAczo eOFsjwCUzGbOO9V6aM3ysqBWDIhzWGNjXkiNMlzYYQ== X-Google-Smtp-Source: APXvYqxPxBqa6Q5trPqt6nLpEjrJvWagv+vXglYbTXmsfxK8aHVbZ7UlOoBk7J5fCcFuJ1NWlwPXJV7IrICxwnh16Ds= X-Received: by 2002:a05:6602:2109:: with SMTP id x9mr108496iox.128.1559042797766; Tue, 28 May 2019 04:26:37 -0700 (PDT) MIME-Version: 1.0 References: <20190527112720.2266-1-ard.biesheuvel@linaro.org> <20190527112720.2266-5-ard.biesheuvel@linaro.org> In-Reply-To: From: Ard Biesheuvel Date: Tue, 28 May 2019 13:26:25 +0200 Message-ID: Subject: Re: [PATCH v3 4/4] gpio: mb86s7x: enable ACPI support To: Linus Walleij Cc: Linux ARM , ACPI Devel Maling List , "open list:GPIO SUBSYSTEM" , Masahisa Kojima , Marc Zyngier , Graeme Gregory , Lorenzo Pieralisi , Mika Westerberg , "Rafael J. Wysocki" , Len Brown Content-Type: text/plain; charset="UTF-8" Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On Tue, 28 May 2019 at 10:34, Linus Walleij wrote: > > On Mon, May 27, 2019 at 1:27 PM Ard Biesheuvel > wrote: > > > Make the mb86s7x GPIO block discoverable via ACPI. In addition, add > > support for ACPI GPIO interrupts routed via platform interrupts, by > > wiring the two together via the to_irq() gpiochip callback. > > > > Reviewed-by: Mika Westerberg > > Signed-off-by: Ard Biesheuvel > > Reviewed-by: Linus Walleij > Thanks. > I assume you want to merge this through the IRQ tree or the ACPI > tree, so go ahead. > > If you want me to queue the whole thing in the GPIO tree just tell > me (once we have the ACKs in place). > Marc is willing to take the whole thing via the irqchip tree. I'll need to apply some tweaks though, so I'll send out a v4 shortly.