From: Asmaa Mnebhi <asmaa@nvidia.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "andy.shevchenko@gmail.com" <andy.shevchenko@gmail.com>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
"kuba@kernel.org" <kuba@kernel.org>,
"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
"bgolaszewski@baylibre.com" <bgolaszewski@baylibre.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"rjw@rjwysocki.net" <rjw@rjwysocki.net>,
David Thompson <davthompson@nvidia.com>
Subject: RE: [PATCH v2 1/2] gpio: mlxbf2: Introduce IRQ support
Date: Wed, 22 Sep 2021 14:16:40 +0000 [thread overview]
Message-ID: <CH2PR12MB38951F1A008AE68A6FE7ED96D7A29@CH2PR12MB3895.namprd12.prod.outlook.com> (raw)
In-Reply-To: <YUpdjh8dtjz29TWU@lunn.ch>
> +static int
> +mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) {
> +
> + switch (type & IRQ_TYPE_SENSE_MASK) {
> + case IRQ_TYPE_EDGE_BOTH:
> + fall = true;
> + rise = true;
> + break;
> + case IRQ_TYPE_EDGE_RISING:
> + rise = true;
> + break;
> + case IRQ_TYPE_EDGE_FALLING:
> + fall = true;
> + break;
> + default:
> + return -EINVAL;
> + }
> What PHY are you using? I think every one i've looked at are
> level triggered, not edge. Using an edge interrupt might work 99%
> of the time, but when the timing is just wrong, you can loose an interrupt.
> Which might mean phylib thinks the link is down, when it fact it is up.
> You will need to unplug and replug to recover from that.
It is the micrel PHY KSZ9031 so it is an active low level interrupt.
Here, IRQ_TYPE_EDGE* macros are mainly used to decide whether to write the
YU_GPIO_CAUSE_FALL_EN register vs the YU_GPIO_CAUSE_RISE_EN register.
These 2 registers are used in both LEVEL/EDGE interrupts.
So I will add back the IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_LEVEL_HIGH as I
did before to configure YU_GPIO_CAUSE_FALL_EN and
YU_GPIO_CAUSE_HIGH_EN respectively. The PHY interrupt signal is physically
Connected to an open drain GPIO pin so software only needs to set
YU_GPIO_CAUSE_FALL_EN register in this case.
Thanks.
Asmaa
next prev parent reply other threads:[~2021-09-22 14:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 21:22 [PATCH v2 0/2] gpio: mlxbf2: Introduce proper interrupt handling Asmaa Mnebhi
2021-09-20 21:22 ` [PATCH v2 1/2] gpio: mlxbf2: Introduce IRQ support Asmaa Mnebhi
2021-09-21 22:32 ` Andrew Lunn
2021-09-22 14:16 ` Asmaa Mnebhi [this message]
2021-09-22 14:57 ` Andrew Lunn
2021-09-23 12:43 ` Asmaa Mnebhi
2021-09-23 14:44 ` Andrew Lunn
2021-09-20 21:22 ` [PATCH v2 2/2] net: mellanox: mlxbf_gige: Replace non-standard interrupt handling Asmaa Mnebhi
2021-09-21 22:29 ` Andrew Lunn
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