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Thu, 16 Sep 2021 15:48:52 +0000 From: Asmaa Mnebhi To: Andrew Lunn CC: "andy.shevchenko@gmail.com" , "linux-gpio@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "kuba@kernel.org" , "linus.walleij@linaro.org" , "bgolaszewski@baylibre.com" , "davem@davemloft.net" , "rjw@rjwysocki.net" , David Thompson Subject: RE: [PATCH v1 1/2] gpio: mlxbf2: Introduce IRQ support Thread-Topic: [PATCH v1 1/2] gpio: mlxbf2: Introduce IRQ support Thread-Index: AQHXqoEVVyA+enuCGUKWJgFkwmB1oKumsuKAgAABitA= Date: Thu, 16 Sep 2021 15:48:51 +0000 Message-ID: References: <20210915222847.10239-1-asmaa@nvidia.com> <20210915222847.10239-2-asmaa@nvidia.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: lunn.ch; dkim=none (message not signed) header.d=none;lunn.ch; dmarc=none action=none header.from=nvidia.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bc52171c-c330-4aa9-7d8c-08d979297b86 x-ms-traffictypediagnostic: CH2PR12MB4891: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CH2PR12MB3895.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bc52171c-c330-4aa9-7d8c-08d979297b86 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Sep 2021 15:48:52.1108 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: +Q5t27dCDTPBbNtSiFPb3I2hiAdUU5MAFQbZDWzH4DmwizZnROjuTzjFte9yyXl9a6NwHG2AucOEVQG6+vScEg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4891 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org > + /* Enable PHY interrupt by setting the priority level */ This should be an abstract driver for a collection of GPIO lines. Yes, one of these GPIOs is used for the PHY, but the GPIO driver does not c= are. So please remove this comment. Asmaa>> Done > + val =3D readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); > + val |=3D BIT(offset); > + writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0); What exactly does this do? It appears to clear the interrupt, if i understa= nd mlxbf2_gpio_irq_handler(). I don't know the GPIO framework well enough t= o know if this is correct. It does mean if the interrupt signal is active b= ut masked, and you enable it, you appear to loose the interrupt? Maybe you = want the interrupt to fire as soon as it is enabled? Asmaa>> YU_GPIO_CAUSE_OR_CLRCAUSE - Makes sure the interrupt is initially cleared. = Otherwise, we will not receive further interrupts. YU_GPIO_CAUSE_OR_EVTEN0 - All interrupts are disabled by default. This regi= ster is what actually unmasks/enables the specific interrupt to start "firi= ng". > +static void mlxbf2_gpio_irq_mask(struct irq_data *irqd) { > + mlxbf2_gpio_irq_disable(irqd); > +} > + > +static void mlxbf2_gpio_irq_unmask(struct irq_data *irqd) { > + mlxbf2_gpio_irq_enable(irqd); > +} Do these two functions have any value? Asmaa>> This code is actually not being called. enable/disable is what's being call= ed. So I will remove it. > + switch (type & IRQ_TYPE_SENSE_MASK) { > + case IRQ_TYPE_EDGE_BOTH: > + case IRQ_TYPE_LEVEL_MASK: > + fall =3D true; > + rise =3D true; > + break; > + case IRQ_TYPE_EDGE_RISING: > + case IRQ_TYPE_LEVEL_HIGH: > + rise =3D true; > + break; > + case IRQ_TYPE_EDGE_FALLING: > + case IRQ_TYPE_LEVEL_LOW: > + fall =3D true; > + break; This looks wrong. You cannot map a level interrupt into an edge. It looks l= ike your hardware only supports edges. If asked to do level, return -EINVAL= . Asmaa>> done > + > + /* The INT_N interrupt level is active low. > + * So enable cause fall bit to detect when GPIO > + * state goes low. > + */ I don't understand this comment. Asmaa>> removed.=20