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From: Sunil V L <sunilvl@ventanamicro.com>
To: Conor Dooley <conor@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH 15/24] clocksource/timer-riscv: Refactor riscv_timer_init_dt()
Date: Mon, 13 Feb 2023 22:52:51 +0530	[thread overview]
Message-ID: <Y+px651SpESUdm4a@sunil-laptop> (raw)
In-Reply-To: <Y+Vdc09bWb9CTXyt@spud>

Hi Conor,

On Thu, Feb 09, 2023 at 08:54:11PM +0000, Conor Dooley wrote:
> Hey Sunil,
> 
> On Mon, Jan 30, 2023 at 11:52:16PM +0530, Sunil V L wrote:
> > Refactor the timer init function such that few things can be shared by
> > both DT and ACPI based platforms.
> > 
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> 
> What did Anup do here? He's not author or co-author, so the SoB chain
> looks incorrect.
> 
When I wanted to refactor, I realized Anup had done similar in his branch for
a different purpose. So, I took some of his changes and I added SOB. Let me
add him in co-developed-by:

> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > ---
> >  drivers/clocksource/timer-riscv.c | 79 +++++++++++++++----------------
> >  1 file changed, 37 insertions(+), 42 deletions(-)
> > 
> > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > index 1b4b36df5484..4016c065a01c 100644
> > --- a/drivers/clocksource/timer-riscv.c
> > +++ b/drivers/clocksource/timer-riscv.c
> > @@ -119,61 +119,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
> >  	return IRQ_HANDLED;
> >  }
> >  
> > -static int __init riscv_timer_init_dt(struct device_node *n)
> > +static int __init riscv_timer_init_common(void)
> >  {
> > -	int cpuid, error;
> > -	unsigned long hartid;
> > -	struct device_node *child;
> > -	struct irq_domain *domain;
> > -
> > -	error = riscv_of_processor_hartid(n, &hartid);
> > -	if (error < 0) {
> > -		pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
> > -			n, hartid);
> > -		return error;
> > -	}
> > -
> > -	cpuid = riscv_hartid_to_cpuid(hartid);
> > -	if (cpuid < 0) {
> > -		pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
> > -		return cpuid;
> > -	}
> > -
> > -	if (cpuid != smp_processor_id())
> > -		return 0;
> > +	int error;
> > +	struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode();
> > +	struct irq_domain *domain = NULL;
> >  
> > -	child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> > -	if (child) {
> > -		riscv_timer_cannot_wake_cpu = of_property_read_bool(child,
> > -					"riscv,timer-cannot-wake-cpu");
> > -		of_node_put(child);
> > -	}
> 
> Uhh, where did this code go?
> Unless I've badly missed something, this has vanished in the patch.
> 
Oops! Anup's patch had moved this to a separate DT timer node instead of
cpu node which I didn't realize. Thanks for catching this. Will fix it.

> >  
> > -	domain = NULL;
> > -	child = of_get_compatible_child(n, "riscv,cpu-intc");
> > -	if (!child) {
> > -		pr_err("Failed to find INTC node [%pOF]\n", n);
> > -		return -ENODEV;
> > -	}
> > -	domain = irq_find_host(child);
> > -	of_node_put(child);
> > +	domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY);
> >  	if (!domain) {
> > -		pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
> > +		pr_err("Failed to find INTC node [%pfwP]\n", intc_fwnode);
> >  		return -ENODEV;
> >  	}
> >  
> >  	riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
> >  	if (!riscv_clock_event_irq) {
> > -		pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
> > -		return -ENODEV;
> > +		pr_err("Failed to map timer interrupt for node [%pfwP]\n",
> > +			intc_fwnode);
> >  	}
> >  
> > -	pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
> > -	       __func__, cpuid, hartid);
> >  	error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
> >  	if (error) {
> > -		pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
> > -		       error, cpuid);
> > +		pr_err("clocksource register failed [%d]\n", error);
> 
> If you're changing this, s/register/registration/ to be grammatically
> correct I suppose.
> 
Sure.
> >  		return error;
> >  	}
> >  
> > @@ -199,7 +166,35 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> >  		static_branch_enable(&riscv_sstc_available);
> >  	}
> >  
> > +	pr_info("timer registered using %s\n",
> > +		(static_branch_likely(&riscv_sstc_available)) ?
> > +		"RISC-V Sstc" : "RISC-V SBI");
> 
> Why is this needed? Isn't there a print like 3 lines above here that
> says "Timer interrupt in S-mode is available via sstc extension"?
> 
Yes, will remove it.

> > +
> >  	return error;
> >  }
> >  
> > +static int __init riscv_timer_init_dt(struct device_node *n)
> > +{
> > +	int cpuid, error;
> > +	unsigned long hartid;
> > +
> > +	error = riscv_of_processor_hartid(n, &hartid);
> > +	if (error < 0) {
> > +		pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
> 
> While you're already moving this, may as well fix the grammar IMO.
> s/Not valid/Invalid/
>
Okay

Thanks!
Sunil 

  reply	other threads:[~2023-02-13 17:23 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-30 18:22 [PATCH 00/24] Add basic ACPI support for RISC-V Sunil V L
2023-01-30 18:22 ` [PATCH 01/24] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-01-30 18:22 ` [PATCH 02/24] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-02-08 19:59   ` Conor Dooley
2023-02-13  5:13     ` Sunil V L
2023-01-30 18:22 ` [PATCH 03/24] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-01-30 18:22 ` [PATCH 04/24] RISC-V: ACPI: Add empty headers to enable ACPI core Sunil V L
2023-02-08 19:55   ` Conor Dooley
2023-01-30 18:22 ` [PATCH 05/24] RISC-V: ACPI: Add basic functions to build " Sunil V L
2023-02-08 20:58   ` Conor Dooley
2023-02-13 15:16     ` Sunil V L
2023-01-30 18:22 ` [PATCH 06/24] RISC-V: ACPI: Add PCI " Sunil V L
2023-02-08 21:26   ` Conor Dooley
2023-02-13 15:23     ` Sunil V L
2023-02-13 17:14       ` Conor Dooley
2023-02-13 17:26   ` Jessica Clarke
2023-02-14  4:42     ` Sunil V L
2023-01-30 18:22 ` [PATCH 07/24] RISC-V: ACPI: Enable ACPI build infrastructure Sunil V L
2023-02-08 21:31   ` Conor Dooley
2023-02-13 15:23     ` Sunil V L
2023-01-30 18:22 ` [PATCH 08/24] ACPI: Enable ACPI_PROCESSOR for RISC-V Sunil V L
2023-01-30 18:22 ` [PATCH 09/24] ACPI: OSL: Make should_use_kmap() 0 " Sunil V L
2023-01-30 18:22 ` [PATCH 10/24] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-01-30 18:22 ` [PATCH 11/24] RISC-V: ACPI: irqchip/riscv-intc: Add ACPI support Sunil V L
2023-01-30 23:38   ` Jessica Clarke
2023-01-31  9:11     ` Sunil V L
2023-02-08 21:49   ` Conor Dooley
2023-02-13 15:25     ` Sunil V L
2023-01-30 18:22 ` [PATCH 12/24] RISC-V: ACPI: smpboot: Create wrapper smp_setup() Sunil V L
2023-02-08 21:34   ` Conor Dooley
2023-01-30 18:22 ` [PATCH 13/24] RISC-V: ACPI: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-02-08 22:10   ` Conor Dooley
2023-02-13 15:27     ` Sunil V L
2023-01-30 18:22 ` [PATCH 14/24] RISC-V: ACPI: smpboot: Add function to retrieve the hartid Sunil V L
2023-02-09 20:30   ` Conor Dooley
2023-02-13 17:00     ` Sunil V L
2023-01-30 18:22 ` [PATCH 15/24] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-02-09 20:54   ` Conor Dooley
2023-02-13 17:22     ` Sunil V L [this message]
2023-01-30 18:22 ` [PATCH 16/24] RISC-V: ACPI: clocksource/timer-riscv: Add ACPI support Sunil V L
2023-02-09 20:58   ` Conor Dooley
2023-02-13 17:39     ` Sunil V L
2023-01-30 18:22 ` [PATCH 17/24] ACPI: RISC-V: drivers/acpi: Add RHCT related code Sunil V L
2023-01-30 18:22 ` [PATCH 18/24] RISC-V: ACPI: time.c: Add ACPI support for time_init() Sunil V L
2023-01-30 18:22 ` [PATCH 19/24] RISC-V: ACPI: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-02-09 21:47   ` Conor Dooley
2023-02-13 17:51     ` Sunil V L
2023-01-30 18:22 ` [PATCH 20/24] RISC-V: ACPI: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-02-09 21:13   ` Conor Dooley
2023-02-13 17:42     ` Sunil V L
2023-01-30 18:22 ` [PATCH 21/24] RISC-V: ACPI: Add ACPI initialization in setup_arch() Sunil V L
2023-02-09 21:53   ` Conor Dooley
2023-02-13 17:52     ` Sunil V L
2023-01-30 18:22 ` [PATCH 22/24] RISC-V: ACPI: Enable ACPI in defconfig Sunil V L
2023-01-30 23:47   ` Conor Dooley
2023-01-31  8:41     ` Sunil V L
2023-01-30 18:22 ` [PATCH 23/24] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-02-09 21:54   ` Conor Dooley
2023-02-13 17:53     ` Sunil V L
2023-01-30 18:22 ` [PATCH 24/24] Documentation/kernel-parameters.txt: Add RISC-V for ACPI parameter Sunil V L
2023-02-09  2:02   ` Bagas Sanjaya
2023-02-13 15:29     ` Sunil V L
2023-01-30 19:11 ` [PATCH 00/24] Add basic ACPI support for RISC-V Rafael J. Wysocki
2023-02-08 18:28 ` Conor Dooley
2023-02-08 18:50   ` Conor Dooley
2023-02-13  4:51     ` Sunil V L

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