From: Neil Armstrong <narmstrong@baylibre.com>
To: Maxime Jourdan <mjourdan@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] clk: meson-g12a: add video decoder clocks
Date: Mon, 1 Apr 2019 10:31:21 +0200 [thread overview]
Message-ID: <106e1a7e-9b0d-d071-5413-520a3b90034a@baylibre.com> (raw)
In-Reply-To: <20190319101138.27520-3-mjourdan@baylibre.com>
On 19/03/2019 11:11, Maxime Jourdan wrote:
> Add the necessary clock parts for:
>
> - VDEC_1: used to feed VDEC_1
> - VDEC_HEVC: the "back" part of the VDEC_HEVC block
> - VDEC_HEVCF: the "front" part of the VDEC_HEVC block
>
> In previous SoC generations (GXL, GXBB), there was only one VDEC_HEVC
> clock, which got split in two parts for G12A.
>
> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
> ---
> drivers/clk/meson/g12a.c | 163 +++++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/g12a.h | 8 +-
> 2 files changed, 170 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
> index 3a3134976534..6c762a8b32b9 100644
> --- a/drivers/clk/meson/g12a.c
> +++ b/drivers/clk/meson/g12a.c
> @@ -1495,6 +1495,151 @@ static struct clk_regmap g12a_vpu = {
> },
> };
>
> +/* VDEC clocks */
> +
> +static const char * const g12a_vdec_parent_names[] = {
> + "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
> + "hifi_pll", "gp0_pll",
> +};
> +
> +static struct clk_regmap g12a_vdec_1_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HHI_VDEC_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 9,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "vdec_1_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_names = g12a_vdec_parent_names,
> + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_1_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = HHI_VDEC_CLK_CNTL,
> + .shift = 0,
> + .width = 7,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "vdec_1_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_names = (const char *[]){ "vdec_1_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_1 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = HHI_VDEC_CLK_CNTL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "vdec_1",
> + .ops = &clk_regmap_gate_ops,
> + .parent_names = (const char *[]){ "vdec_1_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_hevcf_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HHI_VDEC2_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 9,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "vdec_hevcf_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_names = g12a_vdec_parent_names,
> + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_hevcf_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = HHI_VDEC2_CLK_CNTL,
> + .shift = 0,
> + .width = 7,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "vdec_hevcf_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_names = (const char *[]){ "vdec_hevcf_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_hevcf = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = HHI_VDEC2_CLK_CNTL,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "vdec_hevcf",
> + .ops = &clk_regmap_gate_ops,
> + .parent_names = (const char *[]){ "vdec_hevcf_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_hevc_sel = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HHI_VDEC2_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 25,
> + .flags = CLK_MUX_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "vdec_hevc_sel",
> + .ops = &clk_regmap_mux_ops,
> + .parent_names = g12a_vdec_parent_names,
> + .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_hevc_div = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = HHI_VDEC2_CLK_CNTL,
> + .shift = 16,
> + .width = 7,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "vdec_hevc_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_names = (const char *[]){ "vdec_hevc_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_vdec_hevc = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = HHI_VDEC2_CLK_CNTL,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data) {
> + .name = "vdec_hevc",
> + .ops = &clk_regmap_gate_ops,
> + .parent_names = (const char *[]){ "vdec_hevc_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> /* VAPB Clock */
>
> static const char * const g12a_vapb_parent_names[] = {
> @@ -2615,6 +2760,15 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
> [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
> [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
> [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
> + [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
> + [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
> + [CLKID_VDEC_1] = &g12a_vdec_1.hw,
> + [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
> + [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
> + [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
> + [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
> + [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
> + [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
> [NR_CLKS] = NULL,
> },
> .num = NR_CLKS,
> @@ -2803,6 +2957,15 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
> &g12a_cpu_clk_trace,
> &g12a_pcie_pll_od,
> &g12a_pcie_pll_dco,
> + &g12a_vdec_1_sel,
> + &g12a_vdec_1_div,
> + &g12a_vdec_1,
> + &g12a_vdec_hevc_sel,
> + &g12a_vdec_hevc_div,
> + &g12a_vdec_hevc,
> + &g12a_vdec_hevcf_sel,
> + &g12a_vdec_hevcf_div,
> + &g12a_vdec_hevcf,
> };
>
> static const struct meson_eeclkc_data g12a_clkc_data = {
> diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
> index 1393a09730a6..39c41af70804 100644
> --- a/drivers/clk/meson/g12a.h
> +++ b/drivers/clk/meson/g12a.h
> @@ -189,8 +189,14 @@
> #define CLKID_PCIE_PLL_DCO 198
> #define CLKID_PCIE_PLL_DCO_DIV2 199
> #define CLKID_PCIE_PLL_OD 200
> +#define CLKID_VDEC_1_SEL 202
> +#define CLKID_VDEC_1_DIV 203
> +#define CLKID_VDEC_HEVC_SEL 205
> +#define CLKID_VDEC_HEVC_DIV 206
> +#define CLKID_VDEC_HEVCF_SEL 208
> +#define CLKID_VDEC_HEVCF_DIV 209
>
> -#define NR_CLKS 202
> +#define NR_CLKS 211
>
> /* include the CLKIDs that have been made part of the DT binding */
> #include <dt-bindings/clock/g12a-clkc.h>
>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
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next prev parent reply other threads:[~2019-04-01 8:31 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 10:11 [PATCH v2 0/2] clk: meson: add video decoder clocks for G12A Maxime Jourdan
2019-03-19 10:11 ` [PATCH v2 1/2] dt-bindings: clk: g12a-clkc: add VDEC clock IDs Maxime Jourdan
2019-03-31 6:40 ` Rob Herring
2019-03-19 10:11 ` [PATCH v2 2/2] clk: meson-g12a: add video decoder clocks Maxime Jourdan
2019-04-01 8:31 ` Neil Armstrong [this message]
2019-04-01 8:31 ` [PATCH v2 0/2] clk: meson: add video decoder clocks for G12A Neil Armstrong
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