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From: Xingyu Chen <xingyu.chen@amlogic.com>
To: Kevin Hilman <khilman@baylibre.com>,
	Neil Armstrong <narmstrong@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Qianggui Song <qianggui.song@amlogic.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Jianxin Pan <jianxin.pan@amlogic.com>,
	linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org,
	Rob Herring <robh+dt@kernel.org>, Jian Hu <jian.hu@amlogic.com>,
	Xingyu Chen <xingyu.chen@amlogic.com>,
	linux-amlogic@lists.infradead.org,
	Jonathan Cameron <jic23@kernel.org>,
	Jerome Brunet <jbrunet@baylibre.com>
Subject: [PATCH] arm64: dts: a1: add saradc controller
Date: Tue, 3 Dec 2019 15:32:12 +0800
Message-ID: <1575358332-44866-1-git-send-email-xingyu.chen@amlogic.com> (raw)

The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs,
so we use the same compatible string.

Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>

---
This patch is based on A1 clock patchset at [0].

[0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com
---
 arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..cad1756 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -93,6 +93,21 @@
 				clock-names = "xtal", "pclk", "baud";
 				status = "disabled";
 			};
+
+			saradc: adc@2c00 {
+				compatible = "amlogic,meson-g12a-saradc",
+					     "amlogic,meson-saradc";
+				reg = <0x0 0x2c00 0x0 0x48>;
+				#io-channel-cells = <1>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>,
+					 <&clkc_periphs CLKID_SARADC>,
+					 <&clkc_periphs CLKID_SARADC_CLK>,
+					 <&clkc_periphs CLKID_SARADC_SEL>;
+				clock-names = "clkin", "core", "adc_clk",
+					      "adc_sel";
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@ff901000 {
-- 
2.7.4


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