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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id p13sm19780863wrn.0.2020.06.24.23.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jun 2020 23:30:45 -0700 (PDT) References: <20200620161422.24114-1-martin.blumenstingl@googlemail.com> User-agent: mu4e 1.3.3; emacs 26.3 From: Jerome Brunet To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Subject: Re: [PATCH] clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 In-reply-to: <20200620161422.24114-1-martin.blumenstingl@googlemail.com> Date: Thu, 25 Jun 2020 08:30:45 +0200 Message-ID: <1j366jbqsq.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Sat 20 Jun 2020 at 18:14, Martin Blumenstingl wrote: > Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't > know the relation between this clock and RGMII Ethernet. It turns out > that fclk_div2 is used as "timing adjustment clock" to generate the RX > delay on the MAC side - which was enabled by u-boot on Odriod-C1. When > using the RX delay on the PHY side or not using a RX delay at all then > this clock can be disabled. > > Signed-off-by: Martin Blumenstingl Applied. Thx _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic