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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id y14sm31335535wrd.84.2019.10.01.06.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 06:15:55 -0700 (PDT) References: <20190919093627.21245-1-narmstrong@baylibre.com> User-agent: mu4e 1.3.3; emacs 26.2 From: Jerome Brunet To: Neil Armstrong Subject: Re: [PATCH 0/3] clk: meson: g12a: fixes for DVFS In-reply-to: <20190919093627.21245-1-narmstrong@baylibre.com> Date: Tue, 01 Oct 2019 15:15:54 +0200 Message-ID: <1jh84sr4hh.fsf@starbuckisacylon.baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191001_061558_450413_5A29AB98 X-CRM114-Status: GOOD ( 10.11 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Thu 19 Sep 2019 at 11:36, Neil Armstrong wrote: > This is the first serie of fixes for DVFS support on G12a: > - Patch 1 fixes a rebase issue where a CLK_SET_RATE_NO_REPARENT > appeared on the wrong clock and a SET_RATE_PARENT went missing > - Patch 2 helps CCF use the right clock tree for the sub 1GHz clock range > - Patch 3 fixes an issue when we enter suspend with a non-SYS_PLL CPU clock, > leading to a SYS_PLL never enabled again > > Neil Armstrong (3): > clk: meson: g12a: fix cpu clock rate setting > clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes > clk: meson: clk-pll: always enable a critical PLL when setting the > rate > > drivers/clk/meson/clk-pll.c | 2 +- > drivers/clk/meson/g12a.c | 13 +++++++++++-- > 2 files changed, 12 insertions(+), 3 deletions(-) Applied the 2 first fixes. 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