[PATCH v2 0/1] Meson8b RGMII Ethernet pin cleanup

[PATCH v2 0/1] Meson8b RGMII Ethernet pin cleanup

[Martin Blumenstingl]

Hi Emiliano, Hi Linus, Hi Jianxin,

could you please test the patch from this series on your Odroid-C1?
I tested it on mine and Ethernet seems to be improve Ethernet transmit
speeds greatly (at the cost of a small drop in receive performance).

Jianxin, can you please give us the description for pin mux register 7
(PERIPHS_PIN_MUX_7) bits 22 and 23 on Meson8b (S805). The public
datasheet doesn't mention them so we're missing the name of the function
and the pin(s) which are controlled by each bit.


Changes since v1 at [0]:
- rebased so it applies on top of "ARM: dts: meson: meson8b: add the CPU
  OPP tables" which will be part of v4.20-rc1 once the arm-soc tree is
  merged into mainline
- updated patch description with more details


[0] http://lists.infradead.org/pipermail/linux-amlogic/2018-May/007274.html


Martin Blumenstingl (1):
  ARM: dts: meson8b: drop eth_txd0_1 and eth_txd1_1 from eth_rgmii_pins

 arch/arm/boot/dts/meson8b.dtsi | 2 --
 1 file changed, 2 deletions(-)

-- 
2.20.1


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[PATCH v2 1/1] ARM: dts: meson8b: drop eth_txd0_1 and eth_txd1_1 from eth_rgmii_pins

[Martin Blumenstingl]

According to the Odroid-C1+ schematics the Ethernet TXD1 signal is
routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6.

The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and
TXD1 can be routed to DIF_2_N instead. GPIO mux register 6 bit 4
configures DIF_2_P as ETH_TXD0, register 6 bit 5 configures DIF_2_N as
ETH_TXD1.
GPIO mux register 7 bit 21 configures GPIOH_5 as ETH_TXD1, register 7
bit 20 configures GPIOH_6 as ETH_TXD0.

The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both
configured as Ethernet TXD0 data line in meson8b.dtsi. Also eth_txd1_0
(GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured as TXD1 data line.

The vendor u-boot sources for Odroid-C1 use the following Ethernet
pinmux configuration:
  SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f);
  SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000);
This translates to the following pin groups in the mainline kernel:
- register 6 bit  0: eth_rxd1 (DIF_0_P)
- register 6 bit  1: eth_rxd0 (DIF_0_N)
- register 6 bit  2: eth_rx_dv (DIF_1_P)
- register 6 bit  3: eth_rx_clk (DIF_1_N)
- register 6 bit  6: eth_tx_en (DIF_3_P)
- register 6 bit  8: eth_ref_clk (DIF_3_N)
- register 6 bit  9: eth_mdc (DIF_4_P)
- register 6 bit 10: eth_mdio_en (DIF_4_N)
- register 6 bit 11: eth_tx_clk (GPIOH_9)
- register 6 bit 12: eth_txd2 (GPIOH_8)
- register 6 bit 13: eth_txd3 (GPIOH_7)
- register 7 bit 20: eth_txd0_0 (GPIOH_6)
- register 7 bit 21: eth_txd1_0 (GPIOH_5)
- register 7 bit 22: currently unknown, might be eth_rxd2 or eth_rxd3
- register 7 bit 23: currently unknown, might be eth_rxd2 or eth_rxd3

Dropping eth_txd0_1 and eth_txd1_1 improves the receive performance.
This is probably due to the eth_txd0 and eth_txd1 signal being routed to
the wrong pins, so data can only be transferred on eth_txd2 and
eth_txd3. However, I have no scope to confirm this assumption.

iperf3 statistics before this change:
- transmitting from Odroid-C1: 741 Mbits/sec (0 retries)
- receiving on Odroid-C1: 199 Mbits/sec (1713 retries)

iperf3 statistics after this change:
- transmitting from Odroid-C1: 667 Mbits/sec (0 retries)
- receiving on Odroid-C1: 750 Mbits/sec (0 retries)

Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Emiliano Ingrassia <ingrassia@epigenesys.com>
Cc: Linus Lüssing <linus.luessing@c0d3.blue>
---
 arch/arm/boot/dts/meson8b.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 22d775460767..ecca36a8678d 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -270,9 +270,7 @@
 				groups = "eth_tx_clk",
 					 "eth_tx_en",
 					 "eth_txd1_0",
-					 "eth_txd1_1",
 					 "eth_txd0_0",
-					 "eth_txd0_1",
 					 "eth_rx_clk",
 					 "eth_rx_dv",
 					 "eth_rxd1",
-- 
2.20.1


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Re: [PATCH v2 0/1] Meson8b RGMII Ethernet pin cleanup

[Jianxin Pan]

Hi Martin, 


PERIPHS_PIN_MUX_7: 
- register 7 bit 22: ETH_RXD3 (DIF_TTL_2_P)
- register 7 bit 23: ETH_RXD2 (DIF_TTL_2_N)

On 2018/12/29 8:08, Martin Blumenstingl wrote:
> Hi Emiliano, Hi Linus, Hi Jianxin,
> 
> could you please test the patch from this series on your Odroid-C1?
> I tested it on mine and Ethernet seems to be improve Ethernet transmit
> speeds greatly (at the cost of a small drop in receive performance).
> 
> Jianxin, can you please give us the description for pin mux register 7
> (PERIPHS_PIN_MUX_7) bits 22 and 23 on Meson8b (S805). The public
> datasheet doesn't mention them so we're missing the name of the function
> and the pin(s) which are controlled by each bit.
> 
> 
> Changes since v1 at [0]:
> - rebased so it applies on top of "ARM: dts: meson: meson8b: add the CPU
>   OPP tables" which will be part of v4.20-rc1 once the arm-soc tree is
>   merged into mainline
> - updated patch description with more details
> 
> 
> [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-May/007274.html
> 
> 
> Martin Blumenstingl (1):
>   ARM: dts: meson8b: drop eth_txd0_1 and eth_txd1_1 from eth_rgmii_pins
> 
>  arch/arm/boot/dts/meson8b.dtsi | 2 --
>  1 file changed, 2 deletions(-)
> 




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Re: [PATCH v2 0/1] Meson8b RGMII Ethernet pin cleanup

[Martin Blumenstingl]

Hi Jianxin,

that was very quick!

On Sat, Dec 29, 2018 at 6:17 AM Jianxin Pan <jianxin.pan@amlogic.com> wrote:
>
> Hi Martin,
>
>
> PERIPHS_PIN_MUX_7:
> - register 7 bit 22: ETH_RXD3 (DIF_TTL_2_P)
> - register 7 bit 23: ETH_RXD2 (DIF_TTL_2_N)
perfect, thank you - that is exactly the information I need to add the
missing bits to the pinctrl-meson8b driver
finally Odroid-C1 won't drop packets when transferring data anymore
and we rely less on the bootloader to set up the pin mux :)

> On 2018/12/29 8:08, Martin Blumenstingl wrote:
> > Hi Emiliano, Hi Linus, Hi Jianxin,
> >
> > could you please test the patch from this series on your Odroid-C1?
> > I tested it on mine and Ethernet seems to be improve Ethernet transmit
> > speeds greatly (at the cost of a small drop in receive performance).
> >
> > Jianxin, can you please give us the description for pin mux register 7
> > (PERIPHS_PIN_MUX_7) bits 22 and 23 on Meson8b (S805). The public
> > datasheet doesn't mention them so we're missing the name of the function
> > and the pin(s) which are controlled by each bit.
I will send an updated series (which will include a pinctrl-meson8b
patch and an updated .dts patch) later on


Regards
Martin

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