From: Neil Armstrong <narmstrong@baylibre.com>
To: khilman@baylibre.com, jbrunet@baylibre.com
Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH v2 4/5] clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
Date: Mon, 26 Aug 2019 09:25:38 +0200 [thread overview]
Message-ID: <20190826072539.27725-5-narmstrong@baylibre.com> (raw)
In-Reply-To: <20190826072539.27725-1-narmstrong@baylibre.com>
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.
But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.
They are set read-only because the early boot stages sets them to select
the CPU0 input clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/g12a.c | 60 ++++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/g12a.h | 2 +-
2 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index e00df17f800a..ea4c791f106d 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -824,6 +824,60 @@ static struct clk_regmap sm1_dsu_final_clk = {
},
};
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
+static struct clk_regmap sm1_cpu1_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cpu1_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_cpu_clk.hw,
+ /* This CPU also have a dedicated clock tree */
+ },
+ .num_parents = 1,
+ },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
+static struct clk_regmap sm1_cpu2_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cpu2_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_cpu_clk.hw,
+ /* This CPU also have a dedicated clock tree */
+ },
+ .num_parents = 1,
+ },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
+static struct clk_regmap sm1_cpu3_clk = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_SYS_CPU_CLK_CNTL6,
+ .mask = 0x1,
+ .shift = 26,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "cpu3_clk",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &g12a_cpu_clk.hw,
+ /* This CPU also have a dedicated clock tree */
+ },
+ .num_parents = 1,
+ },
+};
+
/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
static struct clk_regmap sm1_dsu_clk = {
.data = &(struct clk_regmap_mux_data){
@@ -4576,6 +4630,9 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
[CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
[CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
[CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
+ [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
+ [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
+ [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -4807,6 +4864,9 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
&sm1_dsu_clk_dyn,
&sm1_dsu_final_clk,
&sm1_dsu_clk,
+ &sm1_cpu1_clk,
+ &sm1_cpu2_clk,
+ &sm1_cpu3_clk,
};
static const struct reg_sequence g12a_init_regs[] = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index 6804fcced6b5..9df4068aced1 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -256,7 +256,7 @@
#define CLKID_DSU_CLK_DYN 250
#define CLKID_DSU_CLK_FINAL 251
-#define NR_CLKS 253
+#define NR_CLKS 256
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/g12a-clkc.h>
--
2.22.0
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next prev parent reply other threads:[~2019-08-26 7:27 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-26 7:25 [PATCH v2 0/5] 0/6] arm64: meson-sm1: add support for DVFS Neil Armstrong
2019-08-26 7:25 ` [PATCH v2 1/5] dt-bindings: clk: meson: add sm1 periph clock controller bindings Neil Armstrong
2019-08-26 7:25 ` [PATCH v2 2/5] clk: meson: g12a: add support for SM1 GP1 PLL Neil Armstrong
2019-08-26 7:25 ` [PATCH v2 3/5] clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock Neil Armstrong
2019-08-26 7:25 ` Neil Armstrong [this message]
2019-08-26 7:25 ` [PATCH v2 5/5] arm64: dts: meson-sm1-sei610: enable DVFS Neil Armstrong
2019-08-26 7:26 ` Neil Armstrong
2019-08-26 10:38 ` [PATCH v2 0/5] 0/6] arm64: meson-sm1: add support for DVFS Jerome Brunet
2019-08-27 19:12 ` Kevin Hilman
2019-08-27 22:35 ` Kevin Hilman
2019-08-28 8:11 ` Jerome Brunet
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