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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id q19sm16701186wra.89.2019.09.19.02.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2019 02:36:28 -0700 (PDT) From: Neil Armstrong To: jbrunet@baylibre.com Subject: [PATCH 0/3] clk: meson: g12a: fixes for DVFS Date: Thu, 19 Sep 2019 11:36:24 +0200 Message-Id: <20190919093627.21245-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190919_023632_880784_32587CE9 X-CRM114-Status: UNSURE ( 7.71 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org This is the first serie of fixes for DVFS support on G12a: - Patch 1 fixes a rebase issue where a CLK_SET_RATE_NO_REPARENT appeared on the wrong clock and a SET_RATE_PARENT went missing - Patch 2 helps CCF use the right clock tree for the sub 1GHz clock range - Patch 3 fixes an issue when we enter suspend with a non-SYS_PLL CPU clock, leading to a SYS_PLL never enabled again Neil Armstrong (3): clk: meson: g12a: fix cpu clock rate setting clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes clk: meson: clk-pll: always enable a critical PLL when setting the rate drivers/clk/meson/clk-pll.c | 2 +- drivers/clk/meson/g12a.c | 13 +++++++++++-- 2 files changed, 12 insertions(+), 3 deletions(-) -- 2.22.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic