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From: Neil Armstrong <narmstrong@baylibre.com>
To: jbrunet@baylibre.com
Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Neil Armstrong <narmstrong@baylibre.com>
Subject: [PATCH 3/3] clk: meson: clk-pll: always enable a critical PLL when setting the rate
Date: Thu, 19 Sep 2019 11:38:09 +0200	[thread overview]
Message-ID: <20190919093809.21364-1-narmstrong@baylibre.com> (raw)
In-Reply-To: <20190919093627.21245-1-narmstrong@baylibre.com>

Make sure we always enable a PLL on a set_rate() when the PLL is
flagged as critical.

This fixes the case when the Amlogic G12A SYS_PLL gets disabled by the
PSCI firmware when resuming from suspend-to-memory, in the case
where the CPU was not clocked by the SYS_PLL, but by the fixed PLL
fixed divisors.
In this particular case, when changing the PLL rate, CCF doesn't handle
the fact the PLL could have been disabled in the meantime and set_rate()
only changes the rate and never enables it again.

Fixes: d6e81845b7d9 ("clk: meson: clk-pll: check if the clock is already enabled')
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/meson/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index ddb1e5634739..8c5adccb7959 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -379,7 +379,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	}
 
 	/* If the pll is stopped, bail out now */
-	if (!enabled)
+	if (!(hw->init->flags & CLK_IS_CRITICAL) && !enabled)
 		return 0;
 
 	if (meson_clk_pll_enable(hw)) {
-- 
2.22.0


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  parent reply	other threads:[~2019-09-19  9:38 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-19  9:36 [PATCH 0/3] clk: meson: g12a: fixes for DVFS Neil Armstrong
2019-09-19  9:36 ` [PATCH 1/3] clk: meson: g12a: fix cpu clock rate setting Neil Armstrong
2019-09-19  9:36 ` [PATCH 2/3] clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes Neil Armstrong
2019-09-19  9:38 ` Neil Armstrong [this message]
2019-09-19 13:01   ` [PATCH 3/3] clk: meson: clk-pll: always enable a critical PLL when setting the rate Jerome Brunet
2019-09-19 17:06     ` Stephen Boyd
2019-09-20  8:06       ` Neil Armstrong
2019-09-20 16:52         ` Stephen Boyd
2019-10-01 13:15 ` [PATCH 0/3] clk: meson: g12a: fixes for DVFS Jerome Brunet

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