From: Remi Pommarel <repk@triplefau.lt>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Yue Wang <yue.wang@Amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Rob Herring <robh+dt@kernel.org>
Cc: linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
Remi Pommarel <repk@triplefau.lt>,
linux-kernel@vger.kernel.org,
Jerome Brunet <jbrunet@baylibre.com>
Subject: [PATCH v4 3/7] dt-bindings: PCI: meson: Update PCIE bindings documentation
Date: Wed, 15 Jan 2020 13:29:04 +0100 [thread overview]
Message-ID: <20200115122908.16954-4-repk@triplefau.lt> (raw)
In-Reply-To: <20200115122908.16954-1-repk@triplefau.lt>
Now that a new PHYs has been introduced for AXG SoC family, update
dt bindings documentation.
Please note that this breaks backward compatibility but as not a single
devicetree uses that yet that seems ok.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
.../bindings/pci/amlogic,meson-pcie.txt | 22 ++++++++-----------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
index 84fdc422792e..b6acbe694ffb 100644
--- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -18,7 +18,6 @@ Required properties:
- reg-names: Must be
- "elbi" External local bus interface registers
- "cfg" Meson specific registers
- - "phy" Meson PCIE PHY registers for AXG SoC Family
- "config" PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
@@ -26,13 +25,13 @@ Required properties:
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A or B) RC clock gate
- "general" PCIe Phy clock
- - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
- resets: phandle to the reset lines.
-- reset-names: must contain "phy" "port" and "apb"
- - "phy" Share PHY reset for AXG SoC Family
+- reset-names: must contain "port" and "apb"
- "port" Port A or B reset
- "apb" Share APB reset
-- phys: should contain a phandle to the shared phy for G12A SoC Family
+- phys: should contain a phandle to the PCIE phy
+- phy-names: must contain "pcie"
+
- device_type:
should be "pci". As specified in designware-pcie.txt
@@ -43,9 +42,8 @@ Example configuration:
compatible = "amlogic,axg-pcie", "snps,dw-pcie";
reg = <0x0 0xf9800000 0x0 0x400000
0x0 0xff646000 0x0 0x2000
- 0x0 0xff644000 0x0 0x2000
0x0 0xf9f00000 0x0 0x100000>;
- reg-names = "elbi", "cfg", "phy", "config";
+ reg-names = "elbi", "cfg", "config";
reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
@@ -58,17 +56,15 @@ Example configuration:
ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
clocks = <&clkc CLKID_USB
- &clkc CLKID_MIPI_ENABLE
&clkc CLKID_PCIE_A
&clkc CLKID_PCIE_CML_EN0>;
clock-names = "general",
- "mipi",
"pclk",
"port";
- resets = <&reset RESET_PCIE_PHY>,
- <&reset RESET_PCIE_A>,
+ resets = <&reset RESET_PCIE_A>,
<&reset RESET_PCIE_APB>;
- reset-names = "phy",
- "port",
+ reset-names = "port",
"apb";
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
};
--
2.24.1
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next prev parent reply other threads:[~2020-01-15 12:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-15 12:29 [PATCH v4 0/7] PCI: amlogic: Make PCIe working reliably on AXG platforms Remi Pommarel
2020-01-15 12:29 ` [PATCH v4 1/7] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2020-01-15 12:29 ` [PATCH v4 2/7] dt-bindings: Add AXG shared MIPI/PCIE " Remi Pommarel
2020-01-21 23:05 ` Rob Herring
2020-01-21 23:08 ` Rob Herring
2020-01-15 12:29 ` Remi Pommarel [this message]
2020-01-15 12:29 ` [PATCH v4 4/7] arm64: dts: meson-axg: Add PCIE PHY nodes Remi Pommarel
2020-01-15 12:29 ` [PATCH v4 5/7] phy: amlogic: Add Amlogic AXG MIPI/PCIE PHY Driver Remi Pommarel
2020-01-15 12:29 ` [PATCH v4 6/7] phy: amlogic: Add Amlogic AXG PCIE " Remi Pommarel
2020-01-15 12:29 ` [PATCH v4 7/7] PCI: amlogic: Use AXG PCIE and shared MIPI/PCIE PHYs Remi Pommarel
2020-01-15 12:30 ` Neil Armstrong
2020-01-15 13:40 ` Remi Pommarel
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