* [PATCH v7 1/5] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
2020-01-20 2:58 [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
@ 2020-01-20 2:58 ` Hanjie Lin
2020-01-20 2:58 ` [PATCH v7 2/5] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Hanjie Lin @ 2020-01-20 2:58 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Add the Amlogic A1 Family USB2 PHY Bindings
It supports Host mode only.
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/amlogic,meson-g12a-usb2-phy.yaml | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
index 57d8603..3b7e763 100644
--- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
@@ -14,6 +14,7 @@ properties:
compatible:
enum:
- amlogic,meson-g12a-usb2-phy
+ - amlogic,meson-a1-usb2-phy
reg:
maxItems: 1
@@ -49,6 +50,20 @@ required:
- reset-names
- "#phy-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-a1-usb-ctrl
+
+ then:
+ properties:
+ power-domains:
+ maxItems: 1
+ required:
+ - power-domains
+
examples:
- |
phy@36000 {
--
2.7.4
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v7 2/5] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings
2020-01-20 2:58 [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
2020-01-20 2:58 ` [PATCH v7 1/5] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
@ 2020-01-20 2:58 ` Hanjie Lin
2020-01-27 15:40 ` Rob Herring
2020-01-20 2:58 ` [PATCH v7 3/5] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Hanjie Lin @ 2020-01-20 2:58 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
The Amlogic A1 SoC Family embeds 1 USB Controllers:
- a DWC3 IP configured as Host for USB2 and USB3
A glue connects the controllers to the USB2 PHY of A1 SoC.
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
---
.../bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
index 4efb77b..904b5d7 100644
--- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
+++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml
@@ -22,10 +22,14 @@ description: |
The DWC3 Glue controls the PHY routing and power, an interrupt line is
connected to the Glue to serve as OTG ID change detection.
+ The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
+ host-only mode.
+
properties:
compatible:
enum:
- amlogic,meson-g12a-usb-ctrl
+ - amlogic,meson-a1-usb-ctrl
ranges: true
@@ -84,6 +88,25 @@ required:
- phys
- dr_mode
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-a1-usb-ctrl
+
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ clock-names:
+ items:
+ - const: usb_ctrl
+ - const: usb_bus
+ - const: xtal_usb_ctrl
+ required:
+ - clock-names
+
examples:
- |
usb: usb@ffe09000 {
--
2.7.4
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v7 2/5] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings
2020-01-20 2:58 ` [PATCH v7 2/5] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
@ 2020-01-27 15:40 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-01-27 15:40 UTC (permalink / raw)
To: Hanjie Lin
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Neil Armstrong,
Stephen Boyd, Greg Kroah-Hartman, Michael Turquette, linux-usb,
Yue Wang, Martin Blumenstingl, Jian Hu, Liang Yang, Qiufang Dai,
Xingyu Chen, Kevin Hilman, Carlo Caione, linux-amlogic,
linux-arm-kernel, Jerome Brunet
On Mon, 20 Jan 2020 10:58:03 +0800, Hanjie Lin wrote:
> The Amlogic A1 SoC Family embeds 1 USB Controllers:
> - a DWC3 IP configured as Host for USB2 and USB3
>
> A glue connects the controllers to the USB2 PHY of A1 SoC.
>
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> ---
> .../bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v7 3/5] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
2020-01-20 2:58 [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
2020-01-20 2:58 ` [PATCH v7 1/5] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
2020-01-20 2:58 ` [PATCH v7 2/5] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
@ 2020-01-20 2:58 ` Hanjie Lin
2020-01-20 2:58 ` [PATCH v7 4/5] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Hanjie Lin @ 2020-01-20 2:58 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
This adds support for the USB2 PHY found in the Amlogic A1 SoC Family.
It supports host mode only.
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/phy/amlogic/phy-meson-g12a-usb2.c | 85 +++++++++++++++++++++----------
1 file changed, 59 insertions(+), 26 deletions(-)
diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
index 9065ffc..33296f8 100644
--- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
+++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
@@ -146,11 +146,17 @@
#define RESET_COMPLETE_TIME 1000
#define PLL_RESET_COMPLETE_TIME 100
+enum meson_soc_id {
+ MESON_SOC_G12A = 0,
+ MESON_SOC_A1,
+};
+
struct phy_meson_g12a_usb2_priv {
struct device *dev;
struct regmap *regmap;
struct clk *clk;
struct reset_control *reset;
+ int soc_id;
};
static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
@@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
{
struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
int ret;
+ unsigned int value;
ret = reset_control_reset(priv->reset);
if (ret)
@@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
- regmap_write(priv->regmap, PHY_CTRL_R18,
- FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
- FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
- PHY_CTRL_R18_MPLL_ACG_RANGE);
+ value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
+ FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
+ PHY_CTRL_R18_MPLL_ACG_RANGE;
+
+ if (priv->soc_id == MESON_SOC_A1)
+ value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
+
+ regmap_write(priv->regmap, PHY_CTRL_R18, value);
udelay(PLL_RESET_COMPLETE_TIME);
@@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
- regmap_write(priv->regmap, PHY_CTRL_R4,
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
- FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
- PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
- FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ if (priv->soc_id == MESON_SOC_G12A)
+ regmap_write(priv->regmap, PHY_CTRL_R4,
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
+ FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
+ PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
+ FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
+ else if (priv->soc_id == MESON_SOC_A1) {
+ regmap_write(priv->regmap, PHY_CTRL_R21,
+ PHY_CTRL_R21_USB2_CAL_ACK_EN |
+ PHY_CTRL_R21_USB2_TX_STRG_PD |
+ FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
+
+ /* Analog Settings */
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ }
/* Tuning Disconnect Threshold */
regmap_write(priv->regmap, PHY_CTRL_R3,
@@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
- /* Analog Settings */
- regmap_write(priv->regmap, PHY_CTRL_R14, 0);
- regmap_write(priv->regmap, PHY_CTRL_R13,
- PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
- FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ if (priv->soc_id == MESON_SOC_G12A) {
+ /* Analog Settings */
+ regmap_write(priv->regmap, PHY_CTRL_R14, 0);
+ regmap_write(priv->regmap, PHY_CTRL_R13,
+ PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
+ FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
+ }
return 0;
}
@@ -286,6 +310,8 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
+ priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
+
priv->regmap = devm_regmap_init_mmio(dev, base,
&phy_meson_g12a_usb2_regmap_conf);
if (IS_ERR(priv->regmap))
@@ -321,8 +347,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
}
static const struct of_device_id phy_meson_g12a_usb2_of_match[] = {
- { .compatible = "amlogic,g12a-usb2-phy", },
- { },
+ {
+ .compatible = "amlogic,g12a-usb2-phy",
+ .data = (void *)MESON_SOC_G12A,
+ },
+ {
+ .compatible = "amlogic,a1-usb2-phy",
+ .data = (void *)MESON_SOC_A1,
+ },
+ { /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);
--
2.7.4
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v7 4/5] usb: dwc3: Add Amlogic A1 DWC3 glue
2020-01-20 2:58 [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
` (2 preceding siblings ...)
2020-01-20 2:58 ` [PATCH v7 3/5] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
@ 2020-01-20 2:58 ` Hanjie Lin
2020-01-20 2:58 ` [PATCH v7 5/5] arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller Hanjie Lin
2020-01-31 13:33 ` [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Felipe Balbi
5 siblings, 0 replies; 8+ messages in thread
From: Hanjie Lin @ 2020-01-20 2:58 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Adds support for Amlogic A1 USB Control Glue HW.
The Amlogic A1 SoC Family embeds 1 USB Controllers:
- a DWC3 IP configured as Host for USB2 and USB3
A glue connects the controllers to the USB2 PHY of A1 SoC.
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
drivers/usb/dwc3/dwc3-meson-g12a.c | 172 +++++++++++++++++++++++++------------
1 file changed, 116 insertions(+), 56 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index 8a3ec1a..70d24b9 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -107,10 +107,37 @@ static const char *phy_names[PHY_COUNT] = {
"usb2-phy0", "usb2-phy1", "usb3-phy0",
};
+static struct clk_bulk_data meson_g12a_clocks[] = {
+ { .id = NULL },
+};
+
+static struct clk_bulk_data meson_a1_clocks[] = {
+ { .id = "usb_ctrl" },
+ { .id = "usb_bus" },
+ { .id = "xtal_usb_ctrl" },
+};
+
+struct dwc3_meson_g12a_drvdata {
+ bool otg_switch_supported;
+ struct clk_bulk_data *clks;
+ int num_clks;
+};
+
+static struct dwc3_meson_g12a_drvdata g12a_drvdata = {
+ .otg_switch_supported = true,
+ .clks = meson_g12a_clocks,
+ .num_clks = ARRAY_SIZE(meson_g12a_clocks),
+};
+
+static struct dwc3_meson_g12a_drvdata a1_drvdata = {
+ .otg_switch_supported = false,
+ .clks = meson_a1_clocks,
+ .num_clks = ARRAY_SIZE(meson_a1_clocks),
+};
+
struct dwc3_meson_g12a {
struct device *dev;
struct regmap *regmap;
- struct clk *clk;
struct reset_control *reset;
struct phy *phys[PHY_COUNT];
enum usb_dr_mode otg_mode;
@@ -120,6 +147,7 @@ struct dwc3_meson_g12a {
struct regulator *vbus;
struct usb_role_switch_desc switch_desc;
struct usb_role_switch *role_switch;
+ const struct dwc3_meson_g12a_drvdata *drvdata;
};
static void dwc3_meson_g12a_usb2_set_mode(struct dwc3_meson_g12a *priv,
@@ -151,7 +179,7 @@ static int dwc3_meson_g12a_usb2_init(struct dwc3_meson_g12a *priv)
U2P_R0_POWER_ON_RESET,
U2P_R0_POWER_ON_RESET);
- if (i == USB2_OTG_PHY) {
+ if (priv->drvdata->otg_switch_supported && i == USB2_OTG_PHY) {
regmap_update_bits(priv->regmap,
U2P_R0 + (U2P_REG_SIZE * i),
U2P_R0_ID_PULLUP | U2P_R0_DRV_VBUS,
@@ -295,7 +323,7 @@ static int dwc3_meson_g12a_otg_mode_set(struct dwc3_meson_g12a *priv,
{
int ret;
- if (!priv->phys[USB2_OTG_PHY])
+ if (!priv->drvdata->otg_switch_supported || !priv->phys[USB2_OTG_PHY])
return -EINVAL;
if (mode == PHY_MODE_USB_HOST)
@@ -380,14 +408,60 @@ static struct device *dwc3_meson_g12_find_child(struct device *dev,
return &pdev->dev;
}
+static int dwc3_meson_g12a_otg_init(struct platform_device *pdev,
+ struct dwc3_meson_g12a *priv)
+{
+ enum phy_mode otg_id;
+ int ret, irq;
+ struct device *dev = &pdev->dev;
+
+ if (!priv->drvdata->otg_switch_supported)
+ return 0;
+
+ if (priv->otg_mode == USB_DR_MODE_OTG) {
+ /* Ack irq before registering */
+ regmap_update_bits(priv->regmap, USB_R5,
+ USB_R5_ID_DIG_IRQ, 0);
+
+ irq = platform_get_irq(pdev, 0);
+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ dwc3_meson_g12a_irq_thread,
+ IRQF_ONESHOT, pdev->name, priv);
+ if (ret)
+ return ret;
+ }
+
+ /* Setup OTG mode corresponding to the ID pin */
+ if (priv->otg_mode == USB_DR_MODE_OTG) {
+ otg_id = dwc3_meson_g12a_get_id(priv);
+ if (otg_id != priv->otg_phy_mode) {
+ if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
+ dev_warn(dev, "Failed to switch OTG mode\n");
+ }
+ }
+
+ /* Setup role switcher */
+ priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev,
+ "snps,dwc3");
+ priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2");
+ priv->switch_desc.allow_userspace_control = true;
+ priv->switch_desc.set = dwc3_meson_g12a_role_set;
+ priv->switch_desc.get = dwc3_meson_g12a_role_get;
+
+ priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc);
+ if (IS_ERR(priv->role_switch))
+ dev_warn(dev, "Unable to register Role Switch\n");
+
+ return ret;
+}
+
static int dwc3_meson_g12a_probe(struct platform_device *pdev)
{
struct dwc3_meson_g12a *priv;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
void __iomem *base;
- enum phy_mode otg_id;
- int ret, i, irq;
+ int ret, i;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -409,17 +483,18 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
priv->vbus = NULL;
}
- priv->clk = devm_clk_get(dev, NULL);
- if (IS_ERR(priv->clk))
- return PTR_ERR(priv->clk);
+ priv->drvdata = of_device_get_match_data(&pdev->dev);
- ret = clk_prepare_enable(priv->clk);
+ ret = devm_clk_bulk_get(dev,
+ priv->drvdata->num_clks,
+ priv->drvdata->clks);
if (ret)
return ret;
- devm_add_action_or_reset(dev,
- (void(*)(void *))clk_disable_unprepare,
- priv->clk);
+ ret = clk_bulk_prepare_enable(priv->drvdata->num_clks,
+ priv->drvdata->clks);
+ if (ret)
+ return ret;
platform_set_drvdata(pdev, priv);
priv->dev = dev;
@@ -433,41 +508,28 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
ret = reset_control_reset(priv->reset);
if (ret)
- return ret;
+ goto err_disable_clks;
ret = dwc3_meson_g12a_get_phys(priv);
if (ret)
- return ret;
+ goto err_disable_clks;
if (priv->vbus) {
ret = regulator_enable(priv->vbus);
if (ret)
- return ret;
+ goto err_disable_clks;
}
/* Get dr_mode */
priv->otg_mode = usb_get_dr_mode(dev);
- if (priv->otg_mode == USB_DR_MODE_OTG) {
- /* Ack irq before registering */
- regmap_update_bits(priv->regmap, USB_R5,
- USB_R5_ID_DIG_IRQ, 0);
-
- irq = platform_get_irq(pdev, 0);
- ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
- dwc3_meson_g12a_irq_thread,
- IRQF_ONESHOT, pdev->name, priv);
- if (ret)
- return ret;
- }
-
dwc3_meson_g12a_usb_init(priv);
/* Init PHYs */
for (i = 0 ; i < PHY_COUNT ; ++i) {
ret = phy_init(priv->phys[i]);
if (ret)
- return ret;
+ goto err_disable_clks;
}
/* Set PHY Power */
@@ -478,31 +540,12 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
}
ret = of_platform_populate(np, NULL, NULL, dev);
- if (ret) {
- clk_disable_unprepare(priv->clk);
+ if (ret)
goto err_phys_power;
- }
-
- /* Setup OTG mode corresponding to the ID pin */
- if (priv->otg_mode == USB_DR_MODE_OTG) {
- otg_id = dwc3_meson_g12a_get_id(priv);
- if (otg_id != priv->otg_phy_mode) {
- if (dwc3_meson_g12a_otg_mode_set(priv, otg_id))
- dev_warn(dev, "Failed to switch OTG mode\n");
- }
- }
- /* Setup role switcher */
- priv->switch_desc.usb2_port = dwc3_meson_g12_find_child(dev,
- "snps,dwc3");
- priv->switch_desc.udc = dwc3_meson_g12_find_child(dev, "snps,dwc2");
- priv->switch_desc.allow_userspace_control = true;
- priv->switch_desc.set = dwc3_meson_g12a_role_set;
- priv->switch_desc.get = dwc3_meson_g12a_role_get;
-
- priv->role_switch = usb_role_switch_register(dev, &priv->switch_desc);
- if (IS_ERR(priv->role_switch))
- dev_warn(dev, "Unable to register Role Switch\n");
+ ret = dwc3_meson_g12a_otg_init(pdev, priv);
+ if (ret)
+ goto err_phys_power;
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
@@ -518,6 +561,10 @@ static int dwc3_meson_g12a_probe(struct platform_device *pdev)
for (i = 0 ; i < PHY_COUNT ; ++i)
phy_exit(priv->phys[i]);
+err_disable_clks:
+ clk_bulk_disable_unprepare(priv->drvdata->num_clks,
+ priv->drvdata->clks);
+
return ret;
}
@@ -527,7 +574,8 @@ static int dwc3_meson_g12a_remove(struct platform_device *pdev)
struct device *dev = &pdev->dev;
int i;
- usb_role_switch_unregister(priv->role_switch);
+ if (priv->drvdata->otg_switch_supported)
+ usb_role_switch_unregister(priv->role_switch);
of_platform_depopulate(dev);
@@ -540,6 +588,9 @@ static int dwc3_meson_g12a_remove(struct platform_device *pdev)
pm_runtime_put_noidle(dev);
pm_runtime_set_suspended(dev);
+ clk_bulk_disable_unprepare(priv->drvdata->num_clks,
+ priv->drvdata->clks);
+
return 0;
}
@@ -547,7 +598,8 @@ static int __maybe_unused dwc3_meson_g12a_runtime_suspend(struct device *dev)
{
struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
- clk_disable(priv->clk);
+ clk_bulk_disable_unprepare(priv->drvdata->num_clks,
+ priv->drvdata->clks);
return 0;
}
@@ -556,7 +608,8 @@ static int __maybe_unused dwc3_meson_g12a_runtime_resume(struct device *dev)
{
struct dwc3_meson_g12a *priv = dev_get_drvdata(dev);
- return clk_enable(priv->clk);
+ return clk_bulk_prepare_enable(priv->drvdata->num_clks,
+ priv->drvdata->clks);
}
static int __maybe_unused dwc3_meson_g12a_suspend(struct device *dev)
@@ -619,7 +672,14 @@ static const struct dev_pm_ops dwc3_meson_g12a_dev_pm_ops = {
};
static const struct of_device_id dwc3_meson_g12a_match[] = {
- { .compatible = "amlogic,meson-g12a-usb-ctrl" },
+ {
+ .compatible = "amlogic,meson-g12a-usb-ctrl",
+ .data = &g12a_drvdata,
+ },
+ {
+ .compatible = "amlogic,meson-a1-usb-ctrl",
+ .data = &a1_drvdata,
+ },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwc3_meson_g12a_match);
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v7 5/5] arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller
2020-01-20 2:58 [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
` (3 preceding siblings ...)
2020-01-20 2:58 ` [PATCH v7 4/5] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
@ 2020-01-20 2:58 ` Hanjie Lin
2020-01-31 13:33 ` [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Felipe Balbi
5 siblings, 0 replies; 8+ messages in thread
From: Hanjie Lin @ 2020-01-20 2:58 UTC (permalink / raw)
To: Jerome Brunet, Neil Armstrong, Rob Herring, Greg Kroah-Hartman,
Kevin Hilman
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
Enable USB2 PHY and DWC3 controller for Meson A1 SoC.
Signed-off-by: Yue Wang <yue.wang@amlogic.com>
Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 43 +++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 6fdc0dd..3b7ca50 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -6,6 +6,9 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/meson-a1-power.h>
+#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
+#include <dt-bindings/clock/a1-pll-clkc.h>
+#include <dt-bindings/clock/a1-clkc.h>
/ {
compatible = "amlogic,a1";
@@ -100,6 +103,17 @@
#power-domain-cells = <1>;
status = "okay";
};
+
+ usb2_phy1: phy@40000 {
+ compatible = "amlogic,a1-usb2-phy";
+ clocks = <&clkc_periphs CLKID_XTAL_USB_PHY>;
+ clock-names = "xtal";
+ reg = <0x0 0x40000 0x0 0x2000>;
+ resets = <&reset RESET_USBPHY>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ power-domains = <&pwrc PWRC_USB_ID>;
+ };
};
gic: interrupt-controller@ff901000 {
@@ -114,6 +128,35 @@
#interrupt-cells = <3>;
#address-cells = <0>;
};
+
+ usb: usb@ffe09000 {
+ status = "disabled";
+ compatible = "amlogic,meson-a1-usb-ctrl";
+ reg = <0x0 0xffe09000 0x0 0xa0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc_periphs CLKID_USB_CTRL>,
+ <&clkc_periphs CLKID_USB_BUS>,
+ <&clkc_periphs CLKID_XTAL_USB_CTRL>;
+ clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
+ resets = <&reset RESET_USBCTRL>;
+
+ dr_mode = "host";
+
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+
+ dwc3: usb@ff400000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff400000 0x0 0x100000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_u2_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ };
+ };
};
timer {
--
2.7.4
_______________________________________________
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linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1
2020-01-20 2:58 [PATCH v7 0/5] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
` (4 preceding siblings ...)
2020-01-20 2:58 ` [PATCH v7 5/5] arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller Hanjie Lin
@ 2020-01-31 13:33 ` Felipe Balbi
5 siblings, 0 replies; 8+ messages in thread
From: Felipe Balbi @ 2020-01-31 13:33 UTC (permalink / raw)
To: Hanjie Lin, Jerome Brunet, Neil Armstrong, Rob Herring,
Greg Kroah-Hartman, Kevin Hilman, Kishon Vijay Abraham I
Cc: devicetree, Hanjie Lin, Victor Wan, Jianxin Pan, Stephen Boyd,
Michael Turquette, linux-usb, Yue Wang, Martin Blumenstingl,
Liang Yang, Qiufang Dai, Xingyu Chen, Carlo Caione,
linux-amlogic, linux-arm-kernel, Jian Hu
[-- Attachment #1.1: Type: text/plain, Size: 3285 bytes --]
Hanjie Lin <hanjie.lin@amlogic.com> writes:
> This patchset adds support for USB on Amlogic A1 SoCs.
>
> This patchset is composed with :
> - bindings of the PHY
> - bindings of the USB Control Glue
> - PHY Driver
> - USB Control Glue driver
> - dts of the PHY
> - dts of the USB Controller
>
> The Amlogic A1 USB Complex is composed of :
> - 1 DWC3 USB controller for USB2 Host functionality
> - 1 USB2 PHY for USB2 Host functionality
>
> The USB Control Glue setups the clocks and the reset about DWC3 USB
> controller, and binds to the USB2 PHY. It also configures the 8bit
> UTMI interfaces for the USB2 PHY, including setting USB2 phy mode.
>
> The USB2 PHY driver initializes the phy analog settings, phy PLL
> setup and phy tuning.
>
> This patchset is based on A1 clock/power domain/reset series at [0].
>
> Changes since v1:[1]
> - integrate glue and phy drivers into g12a's
>
> Changes since v2:[2]
> - modify amlogic,meson-g12a-usb-ctrl.yaml with dt_binding_check tool
> - phy/glue driver use of_device_get_match_data to distinguish A1 from G12A
>
> Changes since v3:[3]
> - fix bindings mistakes of the PHY according Rob's comments
> - fix bindings mistakes of the USB Control Glue according Rob's comments
> - phy driver add xtal_usb_phy clock which moved from glue driver
> - glue driver use otg_mode instead of soc_id to support otg function
>
> Changes since v4:[4]
> - phy driver revert reset-names changes
> - phy driver change clock name to "xtal" to consistent with g12a
> - glue driver add drvdata otg_switch_supported
>
> Changes since v5:[5]
> - integrate phy bindings into g12a
> - modify glue bindings format according to martin's advices
> - glue driver add dwc3_meson_g12a_otg_init() do otg related work
> - glue driver add clk_bulk_disable_unprepare() in remove
>
> Changes since v6:[6]
> - fix glue bindings dt_check_bindings error.
> - squash phy and glue dts patches and set usb status to disabled default
>
> [0]
> https://patchwork.kernel.org/project/linux-amlogic/list/?series=185477
> https://patchwork.kernel.org/project/linux-amlogic/list/?series=180055
> https://patchwork.kernel.org/project/linux-amlogic/list/?series=189643
>
> [1] : https://lore.kernel.org/linux-amlogic/1574405757-76184-1-git-send-email-hanjie.lin@amlogic.com
>
> [2] : https://lore.kernel.org/linux-amlogic/1576636944-196192-1-git-send-email-hanjie.lin@amlogic.com
>
> [3] : https://lore.kernel.org/linux-amlogic/1577428606-69855-1-git-send-email-hanjie.lin@amlogic.com
>
> [4] : https://lore.kernel.org/linux-amlogic/1578537045-23260-1-git-send-email-hanjie.lin@amlogic.com
>
> [5] : https://lore.kernel.org/linux-amlogic/1578634957-54826-1-git-send-email-hanjie.lin@amlogic.com
>
> [6] : https://lore.kernel.org/linux-amlogic/1579220504-110067-1-git-send-email-hanjie.lin@amlogic.com
>
> Hanjie Lin (5):
> dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
> dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings
> phy: amlogic: Add Amlogic A1 USB2 PHY Driver
> usb: dwc3: Add Amlogic A1 DWC3 glue
> arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller
I have taken dwc3 bindings and dwc3 patch. PHY parts should go via Kishon
--
balbi
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