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[2003:f1:3739:6800:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id j24sm706741edp.22.2020.06.29.13.39.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jun 2020 13:39:10 -0700 (PDT) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org Subject: [PATCH 0/2] clk: meson8b: add two missing gate clocks Date: Mon, 29 Jun 2020 22:39:02 +0200 Message-Id: <20200629203904.2989007-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, narmstrong@baylibre.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org While trying to figure out how to set up the video clocks on the 32-bit SoCs I found that the current clock tree is missing two gates. This adds the missing gates based on evidence found in the public S805 datasheet, the GXBB clock driver and 3.10 vendor kernel. I didn't add any Fixes tag because this clock tree is still read-only and the HDMI PLL (the top-most clock in this tree) needs more work as well. Martin Blumenstingl (2): clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: add the vclk2_en gate clock drivers/clk/meson/meson8b.c | 60 ++++++++++++++++++++++++++++++------- drivers/clk/meson/meson8b.h | 4 ++- 2 files changed, 53 insertions(+), 11 deletions(-) -- 2.27.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic