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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j2-20020adfd202000000b002285f73f11dsm15361698wrh.81.2022.10.04.04.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 04:11:28 -0700 (PDT) Subject: [PATCH v2 0/2] spi: amlogic: meson-spicc: Use pinctrl to drive CLK line when idle MIME-Version: 1.0 X-b4-tracking: H4sIAKsUPGMC/w3LwQqAIAwA0F+JnRvYior+Rm3VwEwcRRD+ex7f4X2gnIUVluaDzI+oXLGC2gb8Ye POKGs1kCHqjBnwTmjPgJu8qEnQk3MTTzOPpoeanFVGl230R23xDqGUH44k59JlAAAA From: Amjad Ouled-Ameur Date: Tue, 04 Oct 2022 13:10:35 +0200 Message-Id: <20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com> To: Krzysztof Kozlowski , Neil Armstrong , Rob Herring , Martin Blumenstingl , Kevin Hilman , Jerome Brunet , Mark Brown Cc: Neil Armstrong , Da Xue , linux-kernel@vger.kernel.org, Amjad Ouled-Ameur , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1664881888; l=1309; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=VwbFnbT4s6Zrq8loadTmY7dJAn4b8cAtpYSq0vCjfk8=; b=ALRqw7Ymk81F+EKD98wzP8n0lqz1SXA+1jpgAkhjGD0bKd/c1hNj/+juRTPx5/ijY35GLd8dETKn nYvLSD/PAPPoxiqap46KsYni9nHo3VvHdH69c3fyHkfj5lzvZMR1 X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221004_041132_699677_A81C2507 X-CRM114-Status: GOOD ( 11.20 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message. Signed-off-by: Amjad Ouled-Ameur --- Amjad Ouled-Ameur (2): spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states spi: meson-spicc: Use pinctrl to drive CLK line when idle .../bindings/spi/amlogic,meson-gx-spicc.yaml | 15 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 ++++++++ drivers/spi/spi-meson-spicc.c | 39 +++++++++++++++++++++- 3 files changed, 67 insertions(+), 1 deletion(-) --- base-commit: 725737e7c21d2d25a4312c2aaa82a52bd03e3126 change-id: 20221004-up-aml-fix-spi-c2bb7e78e603 Best regards, -- Amjad Ouled-Ameur _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic