From: Yu Tu <yu.tu@amlogic.com>
To: <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <kelvin.zhang@amlogic.com>, <qi.duan@amlogic.com>,
Yu Tu <yu.tu@amlogic.com>
Subject: [PATCH V7 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller
Date: Mon, 17 Apr 2023 14:50:02 +0800 [thread overview]
Message-ID: <20230417065005.24967-2-yu.tu@amlogic.com> (raw)
In-Reply-To: <20230417065005.24967-1-yu.tu@amlogic.com>
Add the S4 PLL clock controller dt-bindings in the s4 SoC family.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
.../bindings/clock/amlogic,s4-pll-clkc.yaml | 50 +++++++++++++++++++
MAINTAINERS | 1 +
.../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 +++++++++++
3 files changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
new file mode 100644
index 000000000000..aeda4861cebe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson S serials PLL Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Yu Tu <yu.tu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,s4-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xtal
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc_pll: clock-controller@fe008000 {
+ compatible = "amlogic,s4-pll-clkc";
+ reg = <0xfe008000 0x1e8>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 809dad977786..56dcd6d85064 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1882,6 +1882,7 @@ L: linux-amlogic@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/clock/amlogic*
F: drivers/clk/meson/
+F: include/dt-bindings/clock/amlogic*
F: include/dt-bindings/clock/gxbb*
F: include/dt-bindings/clock/meson*
diff --git a/include/dt-bindings/clock/amlogic,s4-pll-clkc.h b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
new file mode 100644
index 000000000000..1dcdedb1a6dd
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 3
+#define CLKID_FCLK_DIV3 5
+#define CLKID_FCLK_DIV4 7
+#define CLKID_FCLK_DIV5 9
+#define CLKID_FCLK_DIV7 11
+#define CLKID_FCLK_DIV2P5 13
+#define CLKID_GP0_PLL 15
+#define CLKID_HIFI_PLL 17
+#define CLKID_HDMI_PLL 20
+#define CLKID_MPLL_50M 22
+#define CLKID_MPLL0 25
+#define CLKID_MPLL1 27
+#define CLKID_MPLL2 29
+#define CLKID_MPLL3 31
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */
--
2.33.1
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next prev parent reply other threads:[~2023-04-17 6:51 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 6:50 [PATCH V7 0/4] Add S4 SoC PLL and Peripheral clock controller Yu Tu
2023-04-17 6:50 ` Yu Tu [this message]
2023-04-21 17:49 ` [PATCH V7 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL " Rob Herring
2023-04-17 6:50 ` [PATCH V7 2/4] dt-bindings: clock: document Amlogic S4 SoC peripherals " Yu Tu
2023-04-21 17:50 ` Rob Herring
2023-04-26 10:49 ` Dmitry Rokosov
2023-04-27 8:03 ` Yu Tu
2023-04-27 8:52 ` Dmitry Rokosov
2023-04-27 11:36 ` Neil Armstrong
2023-05-04 8:47 ` Yu Tu
2023-05-04 8:59 ` Yu Tu
2023-04-17 6:50 ` [PATCH V7 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
2023-04-26 11:13 ` Dmitry Rokosov
2023-04-27 8:38 ` Yu Tu
2023-04-27 9:11 ` Dmitry Rokosov
2023-05-04 9:19 ` Yu Tu
2023-04-17 6:50 ` [PATCH V7 4/4] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller Yu Tu
2023-04-26 11:05 ` Dmitry Rokosov
2023-04-27 8:15 ` Yu Tu
2023-04-27 8:42 ` Dmitry Rokosov
2023-05-01 17:37 ` Jerome Brunet
2023-05-04 8:43 ` Yu Tu
2023-04-23 21:33 ` [PATCH V7 0/4] Add S4 SoC PLL and Peripheral " Martin Blumenstingl
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