From: Neil Armstrong <narmstrong@baylibre.com>
To: linux-amlogic@lists.infradead.org
Subject: Re: [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node
Date: Mon, 24 Aug 2020 10:05:19 +0200 [thread overview]
Message-ID: <31d486c0-b039-f45d-50b1-d795c4321c7e@baylibre.com> (raw)
In-Reply-To: <20200815182223.408965-1-martin.blumenstingl@googlemail.com>
On 15/08/2020 20:22, Martin Blumenstingl wrote:
> All IO mapped SoC peripherals should be within the "soc" node. Move the
> L2 cache-controller there as well since it's the only one not following
> this pattern.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> arch/arm/boot/dts/meson.dtsi | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
> index eadb0832bcfc..7649dd1e0b9e 100644
> --- a/arch/arm/boot/dts/meson.dtsi
> +++ b/arch/arm/boot/dts/meson.dtsi
> @@ -11,13 +11,6 @@ / {
> #size-cells = <1>;
> interrupt-parent = <&gic>;
>
> - L2: cache-controller@c4200000 {
> - compatible = "arm,pl310-cache";
> - reg = <0xc4200000 0x1000>;
> - cache-unified;
> - cache-level = <2>;
> - };
> -
> soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -172,6 +165,13 @@ timer_abcde: timer@9940 {
> };
> };
>
> + L2: cache-controller@c4200000 {
> + compatible = "arm,pl310-cache";
> + reg = <0xc4200000 0x1000>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> periph: bus@c4300000 {
> compatible = "simple-bus";
> reg = <0xc4300000 0x10000>;
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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next prev parent reply other threads:[~2020-08-24 8:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-15 18:22 [PATCH] ARM: dts: meson: move the L2 cache-controller inside the SoC node Martin Blumenstingl
2020-08-24 8:05 ` Neil Armstrong [this message]
2020-08-24 21:15 ` Kevin Hilman
2020-08-24 21:16 ` Kevin Hilman
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