[PATCH 0/3] pinctrl: meson: g12a fixes

[PATCH 0/3] pinctrl: meson: g12a fixes

[Jerome Brunet]

This patchset fixes the initial pinctrl support added for th g12a SoC
family, which is mainly around the register regions claimed by the
driver.

Linus, would it possible for you to provide a tag with these changes to
Kevin ?

ATM, we can only use the devices for which the pinmux is already set by
the bootloader. Enabling the broken pinctrl driver could cause regressions
in kernelCI. Having a tag, would allow us to start using pinctrl on this
SoC in this cycle, w/o regression. It would be nice :)

Jerome

Jerome Brunet (2):
  dt-bindings: pinctrl: meson: update register descriptions
  pinctrl: meson: add optional region for drive strength

Xingyu Chen (1):
  pinctrl: meson: fix G12A ao pull registers base address

 .../bindings/pinctrl/meson,pinctrl.txt        | 10 ++++----
 drivers/pinctrl/meson/pinctrl-meson.c         | 24 ++++++++++++-------
 drivers/pinctrl/meson/pinctrl-meson.h         |  1 +
 3 files changed, 22 insertions(+), 13 deletions(-)

-- 
2.20.1


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[PATCH 1/3] dt-bindings: pinctrl: meson: update register descriptions

[Jerome Brunet]

like pull-enable, pull should be optional has this region is available on
every controllers. Also, the g12a feature a new region "ds" for the
drive-strength

All this region thing is one big mess. I suspect that there is only one
big GPIO region with holes in it. All registers between the current
regions reads '0' so it is probably just spare space to handle more pins.

Since we need to continue to handle the existing controllers, switching to
one single region now would not simplify things. However, if more
organisation layouts and features keep on being added, we may have to look
at this again

Fixes: 3cd3c83f6752 ("pinctrl: Add compatibles for Amlogic Meson G12A pin controllers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 .../devicetree/bindings/pinctrl/meson,pinctrl.txt      | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 82ead40311f6..a47dd990a8d3 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -23,11 +23,11 @@ The GPIO bank for the controller is represented as a sub-node and it acts as a
 GPIO controller.
 
 Required properties for sub-nodes are:
- - reg: should contain address and size for mux, pull-enable, pull and
-   gpio register sets
- - reg-names: an array of strings describing the "reg" entries. Must
-   contain "mux", "pull" and "gpio". "pull-enable" is optional and
-   when it is missing the "pull" registers are used instead
+ - reg: should contain a list of address and size, one tuple for each entry
+   in reg-names.
+ - reg-names: an array of strings describing the "reg" entries.
+   Must contain "mux" and "gpio".
+   May contain "pull", "pull-enable" and "ds" when appropriate.
  - gpio-controller: identifies the node as a gpio controller
  - #gpio-cells: must be 2
 
-- 
2.20.1


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[PATCH 2/3] pinctrl: meson: fix G12A ao pull registers base address

[Jerome Brunet]

From: Xingyu Chen <xingyu.chen@amlogic.com>

Since Meson G12A SoC, Introduce new ao registers AO_RTI_PULL_UP_EN_REG
and AO_GPIO_O.

These bits of controlling output level are remapped to the new register
AO_GPIO_O, and the AO_GPIO_O_EN_N support only controlling output enable.

These bits of controlling pull enable are remapped to the new register
AO_RTI_PULL_UP_EN_REG, and the AO_RTI_PULL_UP_REG support only controlling
pull type(up/down).

The new layout of ao gpio/pull registers is as follows:
- AO_GPIO_O_EN_N        [offset: 0x9 << 2]
- AO_GPIO_I             [offset: 0xa << 2]
- AO_RTI_PULL_UP_REG    [offset: 0xb << 2]
- AO_RTI_PULL_UP_EN_REG [offset: 0xc << 2]
- AO_GPIO_O             [offset: 0xd << 2]

From above, we can see ao GPIO registers region has been separated by the
ao pull registers. In order to ensure the continuity of the region on
software, the ao GPIO and ao pull registers use the same base address, but
can be identified by the offset.

Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index ea87d739f534..a4ae1ac5369e 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,6 +31,9 @@
  * In some cases the register ranges for pull enable and pull
  * direction are the same and thus there are only 3 register ranges.
  *
+ * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
+ * and pull direction are the same, so there are only 2 register ranges.
+ *
  * For the pull and GPIO configuration every bank uses a contiguous
  * set of bits in the register sets described above; the same register
  * can be shared by more banks with different offsets.
@@ -488,23 +491,22 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
 		return PTR_ERR(pc->reg_mux);
 	}
 
-	pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
-	if (IS_ERR(pc->reg_pull)) {
-		dev_err(pc->dev, "pull registers not found\n");
-		return PTR_ERR(pc->reg_pull);
+	pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
+	if (IS_ERR(pc->reg_gpio)) {
+		dev_err(pc->dev, "gpio registers not found\n");
+		return PTR_ERR(pc->reg_gpio);
 	}
 
+	pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
+	/* Use gpio region if pull one is not present */
+	if (IS_ERR(pc->reg_pull))
+		pc->reg_pull = pc->reg_gpio;
+
 	pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
 	/* Use pull region if pull-enable one is not present */
 	if (IS_ERR(pc->reg_pullen))
 		pc->reg_pullen = pc->reg_pull;
 
-	pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
-	if (IS_ERR(pc->reg_gpio)) {
-		dev_err(pc->dev, "gpio registers not found\n");
-		return PTR_ERR(pc->reg_gpio);
-	}
-
 	return 0;
 }
 
-- 
2.20.1


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[PATCH 3/3] pinctrl: meson: add optional region for drive strength

[Jerome Brunet]

On the G12a, there is a new 'region' to handle the drive-strength.
This is optional since the older do not have this.

Fixes: 29ae0952e85f ("pinctrl: meson-g12a: add pinctrl driver support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/pinctrl/meson/pinctrl-meson.c | 6 ++++++
 drivers/pinctrl/meson/pinctrl-meson.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index a4ae1ac5369e..96a4a72708e4 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -507,6 +507,12 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
 	if (IS_ERR(pc->reg_pullen))
 		pc->reg_pullen = pc->reg_pull;
 
+	pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
+	if (IS_ERR(pc->reg_ds)) {
+		dev_dbg(pc->dev, "ds registers not found - skipping\n");
+		pc->reg_ds = NULL;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index eff61ea1c67e..5eaab925f427 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -120,6 +120,7 @@ struct meson_pinctrl {
 	struct regmap *reg_pullen;
 	struct regmap *reg_pull;
 	struct regmap *reg_gpio;
+	struct regmap *reg_ds;
 	struct gpio_chip chip;
 	struct device_node *of_node;
 };
-- 
2.20.1


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Re: [PATCH 0/3] pinctrl: meson: g12a fixes

[Linus Walleij]

On Thu, Jan 17, 2019 at 11:23 AM Jerome Brunet <jbrunet@baylibre.com> wrote:

> This patchset fixes the initial pinctrl support added for th g12a SoC
> family, which is mainly around the register regions claimed by the
> driver.
>
> Linus, would it possible for you to provide a tag with these changes to
> Kevin ?

https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-meson-fixes

> ATM, we can only use the devices for which the pinmux is already set by
> the bootloader. Enabling the broken pinctrl driver could cause regressions
> in kernelCI. Having a tag, would allow us to start using pinctrl on this
> SoC in this cycle, w/o regression. It would be nice :)

When you say "this cycle" do you mean I should target fixes (v5.0-rcN)
or next (v5.1) with these patches?

Yours,
Linus Walleij

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Re: [PATCH 0/3] pinctrl: meson: g12a fixes

[Jerome Brunet]

On Mon, 2019-01-21 at 14:53 +0100, Linus Walleij wrote:
> On Thu, Jan 17, 2019 at 11:23 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
> 
> > This patchset fixes the initial pinctrl support added for th g12a SoC
> > family, which is mainly around the register regions claimed by the
> > driver.
> > 
> > Linus, would it possible for you to provide a tag with these changes to
> > Kevin ?
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-meson-fixes
> 
> > ATM, we can only use the devices for which the pinmux is already set by
> > the bootloader. Enabling the broken pinctrl driver could cause regressions
> > in kernelCI. Having a tag, would allow us to start using pinctrl on this
> > SoC in this cycle, w/o regression. It would be nice :)
> 
> When you say "this cycle" do you mean I should target fixes (v5.0-rcN)
> or next (v5.1) with these patches?

I was referring to the 5.1 release but it is a good question, I did not really
think about 5.0.

Those changes are mainly fixes, so guess it could go in the 5.0 but support
for this SoC is still in its early stages, so either way is fine by me. 

Whatever is simpler for you I guess ;)

> 
> Yours,
> Linus Walleij



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Re: [PATCH 0/3] pinctrl: meson: g12a fixes

[Kevin Hilman]

Jerome Brunet <jbrunet@baylibre.com> writes:

> On Mon, 2019-01-21 at 14:53 +0100, Linus Walleij wrote:
>> On Thu, Jan 17, 2019 at 11:23 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
>> 
>> > This patchset fixes the initial pinctrl support added for th g12a SoC
>> > family, which is mainly around the register regions claimed by the
>> > driver.
>> > 
>> > Linus, would it possible for you to provide a tag with these changes to
>> > Kevin ?
>> 
>> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-meson-fixes
>> 
>> > ATM, we can only use the devices for which the pinmux is already set by
>> > the bootloader. Enabling the broken pinctrl driver could cause regressions
>> > in kernelCI. Having a tag, would allow us to start using pinctrl on this
>> > SoC in this cycle, w/o regression. It would be nice :)
>> 
>> When you say "this cycle" do you mean I should target fixes (v5.0-rcN)
>> or next (v5.1) with these patches?
>
> I was referring to the 5.1 release but it is a good question, I did not really
> think about 5.0.
>
> Those changes are mainly fixes, so guess it could go in the 5.0 but support
> for this SoC is still in its early stages, so either way is fine by me. 
>
> Whatever is simpler for you I guess ;)

If it's not too late, v5.0-rc is simpler for me as it means not having
to deal with this as a dependency branch/tag.

Kevin

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Re: [PATCH 0/3] pinctrl: meson: g12a fixes

[Linus Walleij]

On Mon, Jan 21, 2019 at 4:36 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
> On Mon, 2019-01-21 at 14:53 +0100, Linus Walleij wrote:
> > On Thu, Jan 17, 2019 at 11:23 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
> >
> > > This patchset fixes the initial pinctrl support added for th g12a SoC
> > > family, which is mainly around the register regions claimed by the
> > > driver.
> > >
> > > Linus, would it possible for you to provide a tag with these changes to
> > > Kevin ?
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-meson-fixes
> >
> > > ATM, we can only use the devices for which the pinmux is already set by
> > > the bootloader. Enabling the broken pinctrl driver could cause regressions
> > > in kernelCI. Having a tag, would allow us to start using pinctrl on this
> > > SoC in this cycle, w/o regression. It would be nice :)
> >
> > When you say "this cycle" do you mean I should target fixes (v5.0-rcN)
> > or next (v5.1) with these patches?
>
> I was referring to the 5.1 release but it is a good question, I did not really
> think about 5.0.
>
> Those changes are mainly fixes, so guess it could go in the 5.0 but support
> for this SoC is still in its early stages, so either way is fine by me.
>
> Whatever is simpler for you I guess ;)

I already merged it for devel and other stuff on top so it will be for v5.1
as it looks now.

Yours,
Linus Walleij

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Re: [PATCH 0/3] pinctrl: meson: g12a fixes

[Kevin Hilman]

Linus Walleij <linus.walleij@linaro.org> writes:

> On Mon, Jan 21, 2019 at 4:36 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>> On Mon, 2019-01-21 at 14:53 +0100, Linus Walleij wrote:
>> > On Thu, Jan 17, 2019 at 11:23 AM Jerome Brunet <jbrunet@baylibre.com> wrote:
>> >
>> > > This patchset fixes the initial pinctrl support added for th g12a SoC
>> > > family, which is mainly around the register regions claimed by the
>> > > driver.
>> > >
>> > > Linus, would it possible for you to provide a tag with these changes to
>> > > Kevin ?
>> >
>> > https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-meson-fixes
>> >
>> > > ATM, we can only use the devices for which the pinmux is already set by
>> > > the bootloader. Enabling the broken pinctrl driver could cause regressions
>> > > in kernelCI. Having a tag, would allow us to start using pinctrl on this
>> > > SoC in this cycle, w/o regression. It would be nice :)
>> >
>> > When you say "this cycle" do you mean I should target fixes (v5.0-rcN)
>> > or next (v5.1) with these patches?
>>
>> I was referring to the 5.1 release but it is a good question, I did not really
>> think about 5.0.
>>
>> Those changes are mainly fixes, so guess it could go in the 5.0 but support
>> for this SoC is still in its early stages, so either way is fine by me.
>>
>> Whatever is simpler for you I guess ;)
>
> I already merged it for devel and other stuff on top so it will be for v5.1
> as it looks now.

OK, assuming that tag is still valid (and immutable), that works for me.

Kevin

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