[PATCH 0/5] Meson (32-bit): add support for the Mali GPU

[PATCH 0/5] Meson (32-bit): add support for the Mali GPU

[Martin Blumenstingl]

This series adds support for the Mali-450 GPU on Meson8 and Meson8b.
Meson6 uses a Mali-400 GPU but since we don't have a clock driver (and
I don't have a device for testing) Meson6 is left out in this series.

Meson8 uses a Mali-450 MP6 with six pixel processors. Meson8b (as
cost-reduced SoC) uses a Mali-450 MP2 with two pixel processors.
I tested both using the open source lima driver and a patched mesa
from the lima project as well. Since we don't have display support
on the 32-bit SoCs I used off-screen rendering as described in [0].
The result is (for example): [1]

The bootloader (at least on my boards) leaves the Mali clock disabled
by default. The board crashes when trying to access the Mali registers
with the "core" clock disabled.
Thus this series also implements the required clock driver changes. The
Mali clock tree on Meson8b and Meson8m2 is almost identical to the one
on GXBB (see the description of patch #3 for more details). Only Meson8
is slightly different as it doesn't have a glitch-free mux. Patch #2
prepares the meson8b clock driver so we can have different clocks per
SoC.

Dependencies:
- the .dts changes depend on my other series "ARM: dts: meson: add the
  APB/APB2 busses" from [2]
- the .dts changes from this series have no compile-time dependency on
  the clock driver changes because CLKID_MALI was defined in the
  dt-bindings since the first version of the clock driver (but it was
  not used until now).
- the .dts changes from this series have a runtime dependency on the
  clock driver changes (also from this series) if you have a kernel
  patched with the lima driver (without the lima driver there's no
  runtime dependency)

Other notes:
By default the GPU runs off the XTAL clock (24MHz). The lima driver
currently does not update the GPU clock rate. Different frequencies
have to be requested by adding the following properties to the Mali
GPU node (to run it at 510MHz for example):
  assigned-clocks = <&clkc CLKID_MALI>;
  assigned-clock-rates = <510000000>;


[0] https://gitlab.freedesktop.org/lima/web/wikis/home
[1] https://abload.de/img/dump0myic0.png
[2] https://patchwork.kernel.org/cover/10719445/


Martin Blumenstingl (5):
  dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b
    compatible
  clk: meson: meson8b: use a separate clock table for Meson8
  clk: meson: meson8b: add the GPU clock tree
  ARM: dts: meson8: add the Mali-450 MP6 GPU
  ARM: dts: meson8b: add the Mali-450 MP2 GPU

 .../bindings/gpu/arm,mali-utgard.txt          |   6 +
 arch/arm/boot/dts/meson8.dtsi                 |  58 +++
 arch/arm/boot/dts/meson8b.dtsi                |  46 +++
 drivers/clk/meson/meson8b.c                   | 349 +++++++++++++++++-
 drivers/clk/meson/meson8b.h                   |   9 +-
 5 files changed, 461 insertions(+), 7 deletions(-)

-- 
2.19.2


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[PATCH 1/5] dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible

[Martin Blumenstingl]

Add a compatible string for the Mali-450 GPU on Amlogic Meson8 and
Meson8b SoCs. Meson8 uses an "MP6" variant with six pixel processors
while Meson8b (as cost-reduced SoC) uses an "MP2" variant with two pixel
processors. Both have a reset line to bring the GPU into a well-defined
state.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index 63cd91176a68..efa1077a90cb 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -12,6 +12,8 @@ Required properties:
       + allwinner,sun7i-a20-mali
       + allwinner,sun8i-h3-mali
       + allwinner,sun50i-h5-mali
+      + amlogic,meson8-mali
+      + amlogic,meson8b-mali
       + amlogic,meson-gxbb-mali
       + amlogic,meson-gxl-mali
       + rockchip,rk3036-mali
@@ -77,6 +79,10 @@ to specify one more vendor-specific compatible, among:
     Required properties:
       * resets: phandle to the reset line for the GPU
 
+  - amlogic,meson8-mali and amlogic,meson8b-mali
+    Required properties:
+      * resets: phandle to the reset line for the GPU
+
   - Rockchip variants:
     Required properties:
       * resets: phandle to the reset line for the GPU
-- 
2.19.2


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Re: [PATCH 1/5] dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible

[Rob Herring]

On Sat,  8 Dec 2018 18:12:43 +0100, Martin Blumenstingl wrote:
> Add a compatible string for the Mali-450 GPU on Amlogic Meson8 and
> Meson8b SoCs. Meson8 uses an "MP6" variant with six pixel processors
> while Meson8b (as cost-reduced SoC) uses an "MP2" variant with two pixel
> processors. Both have a reset line to bring the GPU into a well-defined
> state.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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[PATCH 2/5] clk: meson: meson8b: use a separate clock table for Meson8

[Martin Blumenstingl]

The Meson8 SoC is slightly different compared to Meson8b and Meson8m2
because it does not have the glitch-free Mali GPU clock mux. For Meson8b
and Meson8m2 there are currently no known differences.

Add a separate clk_hw_onecell_data table for Meson8 so these differences
can be implemented. For now meson8_hw_onecell_data is a clone of our
existing meson8b_hw_onecell_data.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/meson8b.c | 203 ++++++++++++++++++++++++++++++++++--
 1 file changed, 197 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 950d0e548c75..0b9353d8d4fd 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1659,6 +1659,185 @@ static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
 
+static struct clk_hw_onecell_data meson8_hw_onecell_data = {
+	.hws = {
+		[CLKID_XTAL] = &meson8b_xtal.hw,
+		[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
+		[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
+		[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
+		[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
+		[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
+		[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
+		[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
+		[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
+		[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
+		[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
+		[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
+		[CLKID_CLK81] = &meson8b_clk81.hw,
+		[CLKID_DDR]		    = &meson8b_ddr.hw,
+		[CLKID_DOS]		    = &meson8b_dos.hw,
+		[CLKID_ISA]		    = &meson8b_isa.hw,
+		[CLKID_PL301]		    = &meson8b_pl301.hw,
+		[CLKID_PERIPHS]		    = &meson8b_periphs.hw,
+		[CLKID_SPICC]		    = &meson8b_spicc.hw,
+		[CLKID_I2C]		    = &meson8b_i2c.hw,
+		[CLKID_SAR_ADC]		    = &meson8b_sar_adc.hw,
+		[CLKID_SMART_CARD]	    = &meson8b_smart_card.hw,
+		[CLKID_RNG0]		    = &meson8b_rng0.hw,
+		[CLKID_UART0]		    = &meson8b_uart0.hw,
+		[CLKID_SDHC]		    = &meson8b_sdhc.hw,
+		[CLKID_STREAM]		    = &meson8b_stream.hw,
+		[CLKID_ASYNC_FIFO]	    = &meson8b_async_fifo.hw,
+		[CLKID_SDIO]		    = &meson8b_sdio.hw,
+		[CLKID_ABUF]		    = &meson8b_abuf.hw,
+		[CLKID_HIU_IFACE]	    = &meson8b_hiu_iface.hw,
+		[CLKID_ASSIST_MISC]	    = &meson8b_assist_misc.hw,
+		[CLKID_SPI]		    = &meson8b_spi.hw,
+		[CLKID_I2S_SPDIF]	    = &meson8b_i2s_spdif.hw,
+		[CLKID_ETH]		    = &meson8b_eth.hw,
+		[CLKID_DEMUX]		    = &meson8b_demux.hw,
+		[CLKID_AIU_GLUE]	    = &meson8b_aiu_glue.hw,
+		[CLKID_IEC958]		    = &meson8b_iec958.hw,
+		[CLKID_I2S_OUT]		    = &meson8b_i2s_out.hw,
+		[CLKID_AMCLK]		    = &meson8b_amclk.hw,
+		[CLKID_AIFIFO2]		    = &meson8b_aififo2.hw,
+		[CLKID_MIXER]		    = &meson8b_mixer.hw,
+		[CLKID_MIXER_IFACE]	    = &meson8b_mixer_iface.hw,
+		[CLKID_ADC]		    = &meson8b_adc.hw,
+		[CLKID_BLKMV]		    = &meson8b_blkmv.hw,
+		[CLKID_AIU]		    = &meson8b_aiu.hw,
+		[CLKID_UART1]		    = &meson8b_uart1.hw,
+		[CLKID_G2D]		    = &meson8b_g2d.hw,
+		[CLKID_USB0]		    = &meson8b_usb0.hw,
+		[CLKID_USB1]		    = &meson8b_usb1.hw,
+		[CLKID_RESET]		    = &meson8b_reset.hw,
+		[CLKID_NAND]		    = &meson8b_nand.hw,
+		[CLKID_DOS_PARSER]	    = &meson8b_dos_parser.hw,
+		[CLKID_USB]		    = &meson8b_usb.hw,
+		[CLKID_VDIN1]		    = &meson8b_vdin1.hw,
+		[CLKID_AHB_ARB0]	    = &meson8b_ahb_arb0.hw,
+		[CLKID_EFUSE]		    = &meson8b_efuse.hw,
+		[CLKID_BOOT_ROM]	    = &meson8b_boot_rom.hw,
+		[CLKID_AHB_DATA_BUS]	    = &meson8b_ahb_data_bus.hw,
+		[CLKID_AHB_CTRL_BUS]	    = &meson8b_ahb_ctrl_bus.hw,
+		[CLKID_HDMI_INTR_SYNC]	    = &meson8b_hdmi_intr_sync.hw,
+		[CLKID_HDMI_PCLK]	    = &meson8b_hdmi_pclk.hw,
+		[CLKID_USB1_DDR_BRIDGE]	    = &meson8b_usb1_ddr_bridge.hw,
+		[CLKID_USB0_DDR_BRIDGE]	    = &meson8b_usb0_ddr_bridge.hw,
+		[CLKID_MMC_PCLK]	    = &meson8b_mmc_pclk.hw,
+		[CLKID_DVIN]		    = &meson8b_dvin.hw,
+		[CLKID_UART2]		    = &meson8b_uart2.hw,
+		[CLKID_SANA]		    = &meson8b_sana.hw,
+		[CLKID_VPU_INTR]	    = &meson8b_vpu_intr.hw,
+		[CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
+		[CLKID_CLK81_A9]	    = &meson8b_clk81_a9.hw,
+		[CLKID_VCLK2_VENCI0]	    = &meson8b_vclk2_venci0.hw,
+		[CLKID_VCLK2_VENCI1]	    = &meson8b_vclk2_venci1.hw,
+		[CLKID_VCLK2_VENCP0]	    = &meson8b_vclk2_vencp0.hw,
+		[CLKID_VCLK2_VENCP1]	    = &meson8b_vclk2_vencp1.hw,
+		[CLKID_GCLK_VENCI_INT]	    = &meson8b_gclk_venci_int.hw,
+		[CLKID_GCLK_VENCP_INT]	    = &meson8b_gclk_vencp_int.hw,
+		[CLKID_DAC_CLK]		    = &meson8b_dac_clk.hw,
+		[CLKID_AOCLK_GATE]	    = &meson8b_aoclk_gate.hw,
+		[CLKID_IEC958_GATE]	    = &meson8b_iec958_gate.hw,
+		[CLKID_ENC480P]		    = &meson8b_enc480p.hw,
+		[CLKID_RNG1]		    = &meson8b_rng1.hw,
+		[CLKID_GCLK_VENCL_INT]	    = &meson8b_gclk_vencl_int.hw,
+		[CLKID_VCLK2_VENCLMCC]	    = &meson8b_vclk2_venclmcc.hw,
+		[CLKID_VCLK2_VENCL]	    = &meson8b_vclk2_vencl.hw,
+		[CLKID_VCLK2_OTHER]	    = &meson8b_vclk2_other.hw,
+		[CLKID_EDP]		    = &meson8b_edp.hw,
+		[CLKID_AO_MEDIA_CPU]	    = &meson8b_ao_media_cpu.hw,
+		[CLKID_AO_AHB_SRAM]	    = &meson8b_ao_ahb_sram.hw,
+		[CLKID_AO_AHB_BUS]	    = &meson8b_ao_ahb_bus.hw,
+		[CLKID_AO_IFACE]	    = &meson8b_ao_iface.hw,
+		[CLKID_MPLL0]		    = &meson8b_mpll0.hw,
+		[CLKID_MPLL1]		    = &meson8b_mpll1.hw,
+		[CLKID_MPLL2]		    = &meson8b_mpll2.hw,
+		[CLKID_MPLL0_DIV]	    = &meson8b_mpll0_div.hw,
+		[CLKID_MPLL1_DIV]	    = &meson8b_mpll1_div.hw,
+		[CLKID_MPLL2_DIV]	    = &meson8b_mpll2_div.hw,
+		[CLKID_CPU_IN_SEL]	    = &meson8b_cpu_in_sel.hw,
+		[CLKID_CPU_IN_DIV2]	    = &meson8b_cpu_in_div2.hw,
+		[CLKID_CPU_IN_DIV3]	    = &meson8b_cpu_in_div3.hw,
+		[CLKID_CPU_SCALE_DIV]	    = &meson8b_cpu_scale_div.hw,
+		[CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
+		[CLKID_MPLL_PREDIV]	    = &meson8b_mpll_prediv.hw,
+		[CLKID_FCLK_DIV2_DIV]	    = &meson8b_fclk_div2_div.hw,
+		[CLKID_FCLK_DIV3_DIV]	    = &meson8b_fclk_div3_div.hw,
+		[CLKID_FCLK_DIV4_DIV]	    = &meson8b_fclk_div4_div.hw,
+		[CLKID_FCLK_DIV5_DIV]	    = &meson8b_fclk_div5_div.hw,
+		[CLKID_FCLK_DIV7_DIV]	    = &meson8b_fclk_div7_div.hw,
+		[CLKID_NAND_SEL]	    = &meson8b_nand_clk_sel.hw,
+		[CLKID_NAND_DIV]	    = &meson8b_nand_clk_div.hw,
+		[CLKID_NAND_CLK]	    = &meson8b_nand_clk_gate.hw,
+		[CLKID_PLL_FIXED_DCO]	    = &meson8b_fixed_pll_dco.hw,
+		[CLKID_HDMI_PLL_DCO]	    = &meson8b_hdmi_pll_dco.hw,
+		[CLKID_PLL_SYS_DCO]	    = &meson8b_sys_pll_dco.hw,
+		[CLKID_CPU_CLK_DIV2]	    = &meson8b_cpu_clk_div2.hw,
+		[CLKID_CPU_CLK_DIV3]	    = &meson8b_cpu_clk_div3.hw,
+		[CLKID_CPU_CLK_DIV4]	    = &meson8b_cpu_clk_div4.hw,
+		[CLKID_CPU_CLK_DIV5]	    = &meson8b_cpu_clk_div5.hw,
+		[CLKID_CPU_CLK_DIV6]	    = &meson8b_cpu_clk_div6.hw,
+		[CLKID_CPU_CLK_DIV7]	    = &meson8b_cpu_clk_div7.hw,
+		[CLKID_CPU_CLK_DIV8]	    = &meson8b_cpu_clk_div8.hw,
+		[CLKID_ABP_SEL]		    = &meson8b_abp_clk_sel.hw,
+		[CLKID_ABP]		    = &meson8b_abp_clk_gate.hw,
+		[CLKID_PERIPH_SEL]	    = &meson8b_periph_clk_sel.hw,
+		[CLKID_PERIPH]		    = &meson8b_periph_clk_gate.hw,
+		[CLKID_AXI_SEL]		    = &meson8b_axi_clk_sel.hw,
+		[CLKID_AXI]		    = &meson8b_axi_clk_gate.hw,
+		[CLKID_L2_DRAM_SEL]	    = &meson8b_l2_dram_clk_sel.hw,
+		[CLKID_L2_DRAM]		    = &meson8b_l2_dram_clk_gate.hw,
+		[CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
+		[CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
+		[CLKID_VID_PLL_IN_SEL]	    = &meson8b_vid_pll_in_sel.hw,
+		[CLKID_VID_PLL_IN_EN]	    = &meson8b_vid_pll_in_en.hw,
+		[CLKID_VID_PLL_PRE_DIV]	    = &meson8b_vid_pll_pre_div.hw,
+		[CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
+		[CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
+		[CLKID_VCLK_IN_SEL]	    = &meson8b_vclk_in_sel.hw,
+		[CLKID_VCLK_IN_EN]	    = &meson8b_vclk_in_en.hw,
+		[CLKID_VCLK_DIV1]	    = &meson8b_vclk_div1_gate.hw,
+		[CLKID_VCLK_DIV2_DIV]	    = &meson8b_vclk_div2_div.hw,
+		[CLKID_VCLK_DIV2]	    = &meson8b_vclk_div2_div_gate.hw,
+		[CLKID_VCLK_DIV4_DIV]	    = &meson8b_vclk_div4_div.hw,
+		[CLKID_VCLK_DIV4]	    = &meson8b_vclk_div4_div_gate.hw,
+		[CLKID_VCLK_DIV6_DIV]	    = &meson8b_vclk_div6_div.hw,
+		[CLKID_VCLK_DIV6]	    = &meson8b_vclk_div6_div_gate.hw,
+		[CLKID_VCLK_DIV12_DIV]	    = &meson8b_vclk_div12_div.hw,
+		[CLKID_VCLK_DIV12]	    = &meson8b_vclk_div12_div_gate.hw,
+		[CLKID_VCLK2_IN_SEL]	    = &meson8b_vclk2_in_sel.hw,
+		[CLKID_VCLK2_IN_EN]	    = &meson8b_vclk2_clk_in_en.hw,
+		[CLKID_VCLK2_DIV1]	    = &meson8b_vclk2_div1_gate.hw,
+		[CLKID_VCLK2_DIV2_DIV]	    = &meson8b_vclk2_div2_div.hw,
+		[CLKID_VCLK2_DIV2]	    = &meson8b_vclk2_div2_div_gate.hw,
+		[CLKID_VCLK2_DIV4_DIV]	    = &meson8b_vclk2_div4_div.hw,
+		[CLKID_VCLK2_DIV4]	    = &meson8b_vclk2_div4_div_gate.hw,
+		[CLKID_VCLK2_DIV6_DIV]	    = &meson8b_vclk2_div6_div.hw,
+		[CLKID_VCLK2_DIV6]	    = &meson8b_vclk2_div6_div_gate.hw,
+		[CLKID_VCLK2_DIV12_DIV]	    = &meson8b_vclk2_div12_div.hw,
+		[CLKID_VCLK2_DIV12]	    = &meson8b_vclk2_div12_div_gate.hw,
+		[CLKID_CTS_ENCT_SEL]	    = &meson8b_cts_enct_sel.hw,
+		[CLKID_CTS_ENCT]	    = &meson8b_cts_enct.hw,
+		[CLKID_CTS_ENCP_SEL]	    = &meson8b_cts_encp_sel.hw,
+		[CLKID_CTS_ENCP]	    = &meson8b_cts_encp.hw,
+		[CLKID_CTS_ENCI_SEL]	    = &meson8b_cts_enci_sel.hw,
+		[CLKID_CTS_ENCI]	    = &meson8b_cts_enci.hw,
+		[CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
+		[CLKID_HDMI_TX_PIXEL]	    = &meson8b_hdmi_tx_pixel.hw,
+		[CLKID_CTS_ENCL_SEL]	    = &meson8b_cts_encl_sel.hw,
+		[CLKID_CTS_ENCL]	    = &meson8b_cts_encl.hw,
+		[CLKID_CTS_VDAC0_SEL]	    = &meson8b_cts_vdac0_sel.hw,
+		[CLKID_CTS_VDAC0]	    = &meson8b_cts_vdac0.hw,
+		[CLKID_HDMI_SYS_SEL]	    = &meson8b_hdmi_sys_sel.hw,
+		[CLKID_HDMI_SYS_DIV]	    = &meson8b_hdmi_sys_div.hw,
+		[CLKID_HDMI_SYS]	    = &meson8b_hdmi_sys.hw,
+		[CLK_NR_CLKS]		    = NULL,
+	},
+	.num = CLK_NR_CLKS,
+};
+
 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 	.hws = {
 		[CLKID_XTAL] = &meson8b_xtal.hw,
@@ -2132,7 +2311,6 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
 
 static struct meson8b_nb_data meson8b_cpu_nb_data = {
 	.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
-	.onecell_data = &meson8b_hw_onecell_data,
 };
 
 static const struct regmap_config clkc_regmap_config = {
@@ -2141,7 +2319,8 @@ static const struct regmap_config clkc_regmap_config = {
 	.reg_stride     = 4,
 };
 
-static void __init meson8b_clkc_init(struct device_node *np)
+static void __init meson8b_clkc_init_common(struct device_node *np,
+			struct clk_hw_onecell_data *clk_hw_onecell_data)
 {
 	struct meson8b_clk_reset *rstc;
 	const char *notifier_clk_name;
@@ -2192,14 +2371,16 @@ static void __init meson8b_clkc_init(struct device_node *np)
 	 */
 	for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
 		/* array might be sparse */
-		if (!meson8b_hw_onecell_data.hws[i])
+		if (!clk_hw_onecell_data->hws[i])
 			continue;
 
-		ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[i]);
+		ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
 		if (ret)
 			return;
 	}
 
+	meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
+
 	/*
 	 * FIXME we shouldn't program the muxes in notifier handlers. The
 	 * tricky programming sequence will be handled by the forthcoming
@@ -2215,13 +2396,23 @@ static void __init meson8b_clkc_init(struct device_node *np)
 	}
 
 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
-				     &meson8b_hw_onecell_data);
+				     clk_hw_onecell_data);
 	if (ret)
 		pr_err("%s: failed to register clock provider\n", __func__);
 }
 
+static void __init meson8_clkc_init(struct device_node *np)
+{
+	return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
+}
+
+static void __init meson8b_clkc_init(struct device_node *np)
+{
+	return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
+}
+
 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
-		      meson8b_clkc_init);
+		      meson8_clkc_init);
 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
 		      meson8b_clkc_init);
 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
-- 
2.19.2


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Re: [PATCH 2/5] clk: meson: meson8b: use a separate clock table for Meson8

[Neil Armstrong]

On 08/12/2018 18:12, Martin Blumenstingl wrote:
> The Meson8 SoC is slightly different compared to Meson8b and Meson8m2
> because it does not have the glitch-free Mali GPU clock mux. For Meson8b
> and Meson8m2 there are currently no known differences.
> 
> Add a separate clk_hw_onecell_data table for Meson8 so these differences
> can be implemented. For now meson8_hw_onecell_data is a clone of our
> existing meson8b_hw_onecell_data.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/meson/meson8b.c | 203 ++++++++++++++++++++++++++++++++++--
>  1 file changed, 197 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index 950d0e548c75..0b9353d8d4fd 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -1659,6 +1659,185 @@ static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
>  static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
>  static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
>  
> +static struct clk_hw_onecell_data meson8_hw_onecell_data = {
> +	.hws = {
> +		[CLKID_XTAL] = &meson8b_xtal.hw,
> +		[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
> +		[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
> +		[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
> +		[CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
> +		[CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
> +		[CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
> +		[CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
> +		[CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
> +		[CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
> +		[CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
> +		[CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
> +		[CLKID_CLK81] = &meson8b_clk81.hw,
> +		[CLKID_DDR]		    = &meson8b_ddr.hw,
> +		[CLKID_DOS]		    = &meson8b_dos.hw,
> +		[CLKID_ISA]		    = &meson8b_isa.hw,
> +		[CLKID_PL301]		    = &meson8b_pl301.hw,
> +		[CLKID_PERIPHS]		    = &meson8b_periphs.hw,
> +		[CLKID_SPICC]		    = &meson8b_spicc.hw,
> +		[CLKID_I2C]		    = &meson8b_i2c.hw,
> +		[CLKID_SAR_ADC]		    = &meson8b_sar_adc.hw,
> +		[CLKID_SMART_CARD]	    = &meson8b_smart_card.hw,
> +		[CLKID_RNG0]		    = &meson8b_rng0.hw,
> +		[CLKID_UART0]		    = &meson8b_uart0.hw,
> +		[CLKID_SDHC]		    = &meson8b_sdhc.hw,
> +		[CLKID_STREAM]		    = &meson8b_stream.hw,
> +		[CLKID_ASYNC_FIFO]	    = &meson8b_async_fifo.hw,
> +		[CLKID_SDIO]		    = &meson8b_sdio.hw,
> +		[CLKID_ABUF]		    = &meson8b_abuf.hw,
> +		[CLKID_HIU_IFACE]	    = &meson8b_hiu_iface.hw,
> +		[CLKID_ASSIST_MISC]	    = &meson8b_assist_misc.hw,
> +		[CLKID_SPI]		    = &meson8b_spi.hw,
> +		[CLKID_I2S_SPDIF]	    = &meson8b_i2s_spdif.hw,
> +		[CLKID_ETH]		    = &meson8b_eth.hw,
> +		[CLKID_DEMUX]		    = &meson8b_demux.hw,
> +		[CLKID_AIU_GLUE]	    = &meson8b_aiu_glue.hw,
> +		[CLKID_IEC958]		    = &meson8b_iec958.hw,
> +		[CLKID_I2S_OUT]		    = &meson8b_i2s_out.hw,
> +		[CLKID_AMCLK]		    = &meson8b_amclk.hw,
> +		[CLKID_AIFIFO2]		    = &meson8b_aififo2.hw,
> +		[CLKID_MIXER]		    = &meson8b_mixer.hw,
> +		[CLKID_MIXER_IFACE]	    = &meson8b_mixer_iface.hw,
> +		[CLKID_ADC]		    = &meson8b_adc.hw,
> +		[CLKID_BLKMV]		    = &meson8b_blkmv.hw,
> +		[CLKID_AIU]		    = &meson8b_aiu.hw,
> +		[CLKID_UART1]		    = &meson8b_uart1.hw,
> +		[CLKID_G2D]		    = &meson8b_g2d.hw,
> +		[CLKID_USB0]		    = &meson8b_usb0.hw,
> +		[CLKID_USB1]		    = &meson8b_usb1.hw,
> +		[CLKID_RESET]		    = &meson8b_reset.hw,
> +		[CLKID_NAND]		    = &meson8b_nand.hw,
> +		[CLKID_DOS_PARSER]	    = &meson8b_dos_parser.hw,
> +		[CLKID_USB]		    = &meson8b_usb.hw,
> +		[CLKID_VDIN1]		    = &meson8b_vdin1.hw,
> +		[CLKID_AHB_ARB0]	    = &meson8b_ahb_arb0.hw,
> +		[CLKID_EFUSE]		    = &meson8b_efuse.hw,
> +		[CLKID_BOOT_ROM]	    = &meson8b_boot_rom.hw,
> +		[CLKID_AHB_DATA_BUS]	    = &meson8b_ahb_data_bus.hw,
> +		[CLKID_AHB_CTRL_BUS]	    = &meson8b_ahb_ctrl_bus.hw,
> +		[CLKID_HDMI_INTR_SYNC]	    = &meson8b_hdmi_intr_sync.hw,
> +		[CLKID_HDMI_PCLK]	    = &meson8b_hdmi_pclk.hw,
> +		[CLKID_USB1_DDR_BRIDGE]	    = &meson8b_usb1_ddr_bridge.hw,
> +		[CLKID_USB0_DDR_BRIDGE]	    = &meson8b_usb0_ddr_bridge.hw,
> +		[CLKID_MMC_PCLK]	    = &meson8b_mmc_pclk.hw,
> +		[CLKID_DVIN]		    = &meson8b_dvin.hw,
> +		[CLKID_UART2]		    = &meson8b_uart2.hw,
> +		[CLKID_SANA]		    = &meson8b_sana.hw,
> +		[CLKID_VPU_INTR]	    = &meson8b_vpu_intr.hw,
> +		[CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
> +		[CLKID_CLK81_A9]	    = &meson8b_clk81_a9.hw,
> +		[CLKID_VCLK2_VENCI0]	    = &meson8b_vclk2_venci0.hw,
> +		[CLKID_VCLK2_VENCI1]	    = &meson8b_vclk2_venci1.hw,
> +		[CLKID_VCLK2_VENCP0]	    = &meson8b_vclk2_vencp0.hw,
> +		[CLKID_VCLK2_VENCP1]	    = &meson8b_vclk2_vencp1.hw,
> +		[CLKID_GCLK_VENCI_INT]	    = &meson8b_gclk_venci_int.hw,
> +		[CLKID_GCLK_VENCP_INT]	    = &meson8b_gclk_vencp_int.hw,
> +		[CLKID_DAC_CLK]		    = &meson8b_dac_clk.hw,
> +		[CLKID_AOCLK_GATE]	    = &meson8b_aoclk_gate.hw,
> +		[CLKID_IEC958_GATE]	    = &meson8b_iec958_gate.hw,
> +		[CLKID_ENC480P]		    = &meson8b_enc480p.hw,
> +		[CLKID_RNG1]		    = &meson8b_rng1.hw,
> +		[CLKID_GCLK_VENCL_INT]	    = &meson8b_gclk_vencl_int.hw,
> +		[CLKID_VCLK2_VENCLMCC]	    = &meson8b_vclk2_venclmcc.hw,
> +		[CLKID_VCLK2_VENCL]	    = &meson8b_vclk2_vencl.hw,
> +		[CLKID_VCLK2_OTHER]	    = &meson8b_vclk2_other.hw,
> +		[CLKID_EDP]		    = &meson8b_edp.hw,
> +		[CLKID_AO_MEDIA_CPU]	    = &meson8b_ao_media_cpu.hw,
> +		[CLKID_AO_AHB_SRAM]	    = &meson8b_ao_ahb_sram.hw,
> +		[CLKID_AO_AHB_BUS]	    = &meson8b_ao_ahb_bus.hw,
> +		[CLKID_AO_IFACE]	    = &meson8b_ao_iface.hw,
> +		[CLKID_MPLL0]		    = &meson8b_mpll0.hw,
> +		[CLKID_MPLL1]		    = &meson8b_mpll1.hw,
> +		[CLKID_MPLL2]		    = &meson8b_mpll2.hw,
> +		[CLKID_MPLL0_DIV]	    = &meson8b_mpll0_div.hw,
> +		[CLKID_MPLL1_DIV]	    = &meson8b_mpll1_div.hw,
> +		[CLKID_MPLL2_DIV]	    = &meson8b_mpll2_div.hw,
> +		[CLKID_CPU_IN_SEL]	    = &meson8b_cpu_in_sel.hw,
> +		[CLKID_CPU_IN_DIV2]	    = &meson8b_cpu_in_div2.hw,
> +		[CLKID_CPU_IN_DIV3]	    = &meson8b_cpu_in_div3.hw,
> +		[CLKID_CPU_SCALE_DIV]	    = &meson8b_cpu_scale_div.hw,
> +		[CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
> +		[CLKID_MPLL_PREDIV]	    = &meson8b_mpll_prediv.hw,
> +		[CLKID_FCLK_DIV2_DIV]	    = &meson8b_fclk_div2_div.hw,
> +		[CLKID_FCLK_DIV3_DIV]	    = &meson8b_fclk_div3_div.hw,
> +		[CLKID_FCLK_DIV4_DIV]	    = &meson8b_fclk_div4_div.hw,
> +		[CLKID_FCLK_DIV5_DIV]	    = &meson8b_fclk_div5_div.hw,
> +		[CLKID_FCLK_DIV7_DIV]	    = &meson8b_fclk_div7_div.hw,
> +		[CLKID_NAND_SEL]	    = &meson8b_nand_clk_sel.hw,
> +		[CLKID_NAND_DIV]	    = &meson8b_nand_clk_div.hw,
> +		[CLKID_NAND_CLK]	    = &meson8b_nand_clk_gate.hw,
> +		[CLKID_PLL_FIXED_DCO]	    = &meson8b_fixed_pll_dco.hw,
> +		[CLKID_HDMI_PLL_DCO]	    = &meson8b_hdmi_pll_dco.hw,
> +		[CLKID_PLL_SYS_DCO]	    = &meson8b_sys_pll_dco.hw,
> +		[CLKID_CPU_CLK_DIV2]	    = &meson8b_cpu_clk_div2.hw,
> +		[CLKID_CPU_CLK_DIV3]	    = &meson8b_cpu_clk_div3.hw,
> +		[CLKID_CPU_CLK_DIV4]	    = &meson8b_cpu_clk_div4.hw,
> +		[CLKID_CPU_CLK_DIV5]	    = &meson8b_cpu_clk_div5.hw,
> +		[CLKID_CPU_CLK_DIV6]	    = &meson8b_cpu_clk_div6.hw,
> +		[CLKID_CPU_CLK_DIV7]	    = &meson8b_cpu_clk_div7.hw,
> +		[CLKID_CPU_CLK_DIV8]	    = &meson8b_cpu_clk_div8.hw,
> +		[CLKID_ABP_SEL]		    = &meson8b_abp_clk_sel.hw,
> +		[CLKID_ABP]		    = &meson8b_abp_clk_gate.hw,
> +		[CLKID_PERIPH_SEL]	    = &meson8b_periph_clk_sel.hw,
> +		[CLKID_PERIPH]		    = &meson8b_periph_clk_gate.hw,
> +		[CLKID_AXI_SEL]		    = &meson8b_axi_clk_sel.hw,
> +		[CLKID_AXI]		    = &meson8b_axi_clk_gate.hw,
> +		[CLKID_L2_DRAM_SEL]	    = &meson8b_l2_dram_clk_sel.hw,
> +		[CLKID_L2_DRAM]		    = &meson8b_l2_dram_clk_gate.hw,
> +		[CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
> +		[CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
> +		[CLKID_VID_PLL_IN_SEL]	    = &meson8b_vid_pll_in_sel.hw,
> +		[CLKID_VID_PLL_IN_EN]	    = &meson8b_vid_pll_in_en.hw,
> +		[CLKID_VID_PLL_PRE_DIV]	    = &meson8b_vid_pll_pre_div.hw,
> +		[CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
> +		[CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
> +		[CLKID_VCLK_IN_SEL]	    = &meson8b_vclk_in_sel.hw,
> +		[CLKID_VCLK_IN_EN]	    = &meson8b_vclk_in_en.hw,
> +		[CLKID_VCLK_DIV1]	    = &meson8b_vclk_div1_gate.hw,
> +		[CLKID_VCLK_DIV2_DIV]	    = &meson8b_vclk_div2_div.hw,
> +		[CLKID_VCLK_DIV2]	    = &meson8b_vclk_div2_div_gate.hw,
> +		[CLKID_VCLK_DIV4_DIV]	    = &meson8b_vclk_div4_div.hw,
> +		[CLKID_VCLK_DIV4]	    = &meson8b_vclk_div4_div_gate.hw,
> +		[CLKID_VCLK_DIV6_DIV]	    = &meson8b_vclk_div6_div.hw,
> +		[CLKID_VCLK_DIV6]	    = &meson8b_vclk_div6_div_gate.hw,
> +		[CLKID_VCLK_DIV12_DIV]	    = &meson8b_vclk_div12_div.hw,
> +		[CLKID_VCLK_DIV12]	    = &meson8b_vclk_div12_div_gate.hw,
> +		[CLKID_VCLK2_IN_SEL]	    = &meson8b_vclk2_in_sel.hw,
> +		[CLKID_VCLK2_IN_EN]	    = &meson8b_vclk2_clk_in_en.hw,
> +		[CLKID_VCLK2_DIV1]	    = &meson8b_vclk2_div1_gate.hw,
> +		[CLKID_VCLK2_DIV2_DIV]	    = &meson8b_vclk2_div2_div.hw,
> +		[CLKID_VCLK2_DIV2]	    = &meson8b_vclk2_div2_div_gate.hw,
> +		[CLKID_VCLK2_DIV4_DIV]	    = &meson8b_vclk2_div4_div.hw,
> +		[CLKID_VCLK2_DIV4]	    = &meson8b_vclk2_div4_div_gate.hw,
> +		[CLKID_VCLK2_DIV6_DIV]	    = &meson8b_vclk2_div6_div.hw,
> +		[CLKID_VCLK2_DIV6]	    = &meson8b_vclk2_div6_div_gate.hw,
> +		[CLKID_VCLK2_DIV12_DIV]	    = &meson8b_vclk2_div12_div.hw,
> +		[CLKID_VCLK2_DIV12]	    = &meson8b_vclk2_div12_div_gate.hw,
> +		[CLKID_CTS_ENCT_SEL]	    = &meson8b_cts_enct_sel.hw,
> +		[CLKID_CTS_ENCT]	    = &meson8b_cts_enct.hw,
> +		[CLKID_CTS_ENCP_SEL]	    = &meson8b_cts_encp_sel.hw,
> +		[CLKID_CTS_ENCP]	    = &meson8b_cts_encp.hw,
> +		[CLKID_CTS_ENCI_SEL]	    = &meson8b_cts_enci_sel.hw,
> +		[CLKID_CTS_ENCI]	    = &meson8b_cts_enci.hw,
> +		[CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
> +		[CLKID_HDMI_TX_PIXEL]	    = &meson8b_hdmi_tx_pixel.hw,
> +		[CLKID_CTS_ENCL_SEL]	    = &meson8b_cts_encl_sel.hw,
> +		[CLKID_CTS_ENCL]	    = &meson8b_cts_encl.hw,
> +		[CLKID_CTS_VDAC0_SEL]	    = &meson8b_cts_vdac0_sel.hw,
> +		[CLKID_CTS_VDAC0]	    = &meson8b_cts_vdac0.hw,
> +		[CLKID_HDMI_SYS_SEL]	    = &meson8b_hdmi_sys_sel.hw,
> +		[CLKID_HDMI_SYS_DIV]	    = &meson8b_hdmi_sys_div.hw,
> +		[CLKID_HDMI_SYS]	    = &meson8b_hdmi_sys.hw,
> +		[CLK_NR_CLKS]		    = NULL,
> +	},
> +	.num = CLK_NR_CLKS,
> +};
> +
>  static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
>  	.hws = {
>  		[CLKID_XTAL] = &meson8b_xtal.hw,
> @@ -2132,7 +2311,6 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
>  
>  static struct meson8b_nb_data meson8b_cpu_nb_data = {
>  	.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
> -	.onecell_data = &meson8b_hw_onecell_data,
>  };
>  
>  static const struct regmap_config clkc_regmap_config = {
> @@ -2141,7 +2319,8 @@ static const struct regmap_config clkc_regmap_config = {
>  	.reg_stride     = 4,
>  };
>  
> -static void __init meson8b_clkc_init(struct device_node *np)
> +static void __init meson8b_clkc_init_common(struct device_node *np,
> +			struct clk_hw_onecell_data *clk_hw_onecell_data)
>  {
>  	struct meson8b_clk_reset *rstc;
>  	const char *notifier_clk_name;
> @@ -2192,14 +2371,16 @@ static void __init meson8b_clkc_init(struct device_node *np)
>  	 */
>  	for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
>  		/* array might be sparse */
> -		if (!meson8b_hw_onecell_data.hws[i])
> +		if (!clk_hw_onecell_data->hws[i])
>  			continue;
>  
> -		ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[i]);
> +		ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
>  		if (ret)
>  			return;
>  	}
>  
> +	meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
> +
>  	/*
>  	 * FIXME we shouldn't program the muxes in notifier handlers. The
>  	 * tricky programming sequence will be handled by the forthcoming
> @@ -2215,13 +2396,23 @@ static void __init meson8b_clkc_init(struct device_node *np)
>  	}
>  
>  	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
> -				     &meson8b_hw_onecell_data);
> +				     clk_hw_onecell_data);
>  	if (ret)
>  		pr_err("%s: failed to register clock provider\n", __func__);
>  }
>  
> +static void __init meson8_clkc_init(struct device_node *np)
> +{
> +	return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
> +}
> +
> +static void __init meson8b_clkc_init(struct device_node *np)
> +{
> +	return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
> +}
> +
>  CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
> -		      meson8b_clkc_init);
> +		      meson8_clkc_init);
>  CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
>  		      meson8b_clkc_init);
>  CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
> 

This would happen one day !

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Neil

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[PATCH 3/5] clk: meson: meson8b: add the GPU clock tree

[Martin Blumenstingl]

Add the GPU clock tree on Meson8, Meson8b and Meson8m2.

The GPU clock tree on Meson8b and Meson8m2 is almost identical to the
one one GXBB:
- there's a glitch-free mux at HHI_MALI_CLK_CNTL[31]
- there are two identical parents for this mux: mali_0 and mali_1, each
  with a gate, divider and mux
- the parents of mali_0_sel and mali_1_sel are identical to GXBB except
  there's no GP0_PLL on these 32-bit SoCs

Meson8 is different because it does not have the glitch-free mux.
Instead if only has the mali_0 clock tree. The parents of mali_0_sel are
identical to the ones on Meson8b and Meson8m2.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clk/meson/meson8b.c | 146 ++++++++++++++++++++++++++++++++++++
 drivers/clk/meson/meson8b.h |   9 ++-
 2 files changed, 154 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 0b9353d8d4fd..748552c5f6c8 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1573,6 +1573,135 @@ static struct clk_regmap meson8b_hdmi_sys = {
 	},
 };
 
+/*
+ * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
+ * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
+ * has mali_0 and no glitch-free mux.
+ */
+static const char * const meson8b_mali_0_1_parent_names[] = {
+	"xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3",
+	"fclk_div5"
+};
+
+static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
+
+static struct clk_regmap meson8b_mali_0_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_MALI_CLK_CNTL,
+		.mask = 0x7,
+		.shift = 9,
+		.table = meson8b_mali_0_1_mux_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = meson8b_mali_0_1_parent_names,
+		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
+		/*
+		 * Don't propagate rate changes up because the only changeable
+		 * parents are mpll1 and mpll2 but we need those for audio and
+		 * RGMII (Ethernet). We don't want to change the audio or
+		 * Ethernet clocks when setting the GPU frequency.
+		 */
+		.flags = 0,
+	},
+};
+
+static struct clk_regmap meson8b_mali_0_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_MALI_CLK_CNTL,
+		.shift = 0,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "mali_0_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_mali_0 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_MALI_CLK_CNTL,
+		.bit_idx = 8,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_0",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "mali_0_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_mali_1_sel = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_MALI_CLK_CNTL,
+		.mask = 0x7,
+		.shift = 25,
+		.table = meson8b_mali_0_1_mux_table,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1_sel",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = meson8b_mali_0_1_parent_names,
+		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
+		/*
+		 * Don't propagate rate changes up because the only changeable
+		 * parents are mpll1 and mpll2 but we need those for audio and
+		 * RGMII (Ethernet). We don't want to change the audio or
+		 * Ethernet clocks when setting the GPU frequency.
+		 */
+		.flags = 0,
+	},
+};
+
+static struct clk_regmap meson8b_mali_1_div = {
+	.data = &(struct clk_regmap_div_data){
+		.offset = HHI_MALI_CLK_CNTL,
+		.shift = 16,
+		.width = 7,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1_div",
+		.ops = &clk_regmap_divider_ops,
+		.parent_names = (const char *[]){ "mali_1_sel" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_mali_1 = {
+	.data = &(struct clk_regmap_gate_data){
+		.offset = HHI_MALI_CLK_CNTL,
+		.bit_idx = 24,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali_1",
+		.ops = &clk_regmap_gate_ops,
+		.parent_names = (const char *[]){ "mali_1_div" },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_regmap meson8b_mali = {
+	.data = &(struct clk_regmap_mux_data){
+		.offset = HHI_MALI_CLK_CNTL,
+		.mask = 1,
+		.shift = 31,
+	},
+	.hw.init = &(struct clk_init_data){
+		.name = "mali",
+		.ops = &clk_regmap_mux_ops,
+		.parent_names = (const char *[]){ "mali_0", "mali_1" },
+		.num_parents = 2,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
 /* Everything Else (EE) domain gates */
 
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -1833,6 +1962,9 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
 		[CLKID_HDMI_SYS_SEL]	    = &meson8b_hdmi_sys_sel.hw,
 		[CLKID_HDMI_SYS_DIV]	    = &meson8b_hdmi_sys_div.hw,
 		[CLKID_HDMI_SYS]	    = &meson8b_hdmi_sys.hw,
+		[CLKID_MALI_0_SEL]	    = &meson8b_mali_0_sel.hw,
+		[CLKID_MALI_0_DIV]	    = &meson8b_mali_0_div.hw,
+		[CLKID_MALI]		    = &meson8b_mali_0.hw,
 		[CLK_NR_CLKS]		    = NULL,
 	},
 	.num = CLK_NR_CLKS,
@@ -2012,6 +2144,13 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 		[CLKID_HDMI_SYS_SEL]	    = &meson8b_hdmi_sys_sel.hw,
 		[CLKID_HDMI_SYS_DIV]	    = &meson8b_hdmi_sys_div.hw,
 		[CLKID_HDMI_SYS]	    = &meson8b_hdmi_sys.hw,
+		[CLKID_MALI_0_SEL]	    = &meson8b_mali_0_sel.hw,
+		[CLKID_MALI_0_DIV]	    = &meson8b_mali_0_div.hw,
+		[CLKID_MALI_0]		    = &meson8b_mali_0.hw,
+		[CLKID_MALI_1_SEL]	    = &meson8b_mali_1_sel.hw,
+		[CLKID_MALI_1_DIV]	    = &meson8b_mali_1_div.hw,
+		[CLKID_MALI_1]		    = &meson8b_mali_1.hw,
+		[CLKID_MALI]		    = &meson8b_mali.hw,
 		[CLK_NR_CLKS]		    = NULL,
 	},
 	.num = CLK_NR_CLKS,
@@ -2167,6 +2306,13 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
 	&meson8b_hdmi_sys_sel,
 	&meson8b_hdmi_sys_div,
 	&meson8b_hdmi_sys,
+	&meson8b_mali_0_sel,
+	&meson8b_mali_0_div,
+	&meson8b_mali_0,
+	&meson8b_mali_1_sel,
+	&meson8b_mali_1_div,
+	&meson8b_mali_1,
+	&meson8b_mali,
 };
 
 static const struct meson8b_clk_reset_line {
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 87fba739af81..f212e2304ff5 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -33,6 +33,7 @@
 #define HHI_VID_CLK_CNTL2		0x194 /* 0x65 offset in data sheet */
 #define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
 #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
+#define HHI_MALI_CLK_CNTL		0x1b0 /* 0x6c offset in data sheet */
 #define HHI_HDMI_CLK_CNTL		0x1cc /* 0x73 offset in data sheet */
 #define HHI_NAND_CLK_CNTL		0x25c /* 0x97 offset in data sheet */
 #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
@@ -139,8 +140,14 @@
 #define CLKID_HDMI_SYS_SEL	172
 #define CLKID_HDMI_SYS_DIV	173
 #define CLKID_HDMI_SYS		174
+#define CLKID_MALI_0_SEL	175
+#define CLKID_MALI_0_DIV	176
+#define CLKID_MALI_0		177
+#define CLKID_MALI_1_SEL	178
+#define CLKID_MALI_1_DIV	179
+#define CLKID_MALI_1		180
 
-#define CLK_NR_CLKS		175
+#define CLK_NR_CLKS		181
 
 /*
  * include the CLKID and RESETID that have
-- 
2.19.2


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Re: [PATCH 3/5] clk: meson: meson8b: add the GPU clock tree

[Neil Armstrong]

On 08/12/2018 18:12, Martin Blumenstingl wrote:
> Add the GPU clock tree on Meson8, Meson8b and Meson8m2.
> 
> The GPU clock tree on Meson8b and Meson8m2 is almost identical to the
> one one GXBB:
> - there's a glitch-free mux at HHI_MALI_CLK_CNTL[31]
> - there are two identical parents for this mux: mali_0 and mali_1, each
>   with a gate, divider and mux
> - the parents of mali_0_sel and mali_1_sel are identical to GXBB except
>   there's no GP0_PLL on these 32-bit SoCs
> 
> Meson8 is different because it does not have the glitch-free mux.
> Instead if only has the mali_0 clock tree. The parents of mali_0_sel are
> identical to the ones on Meson8b and Meson8m2.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clk/meson/meson8b.c | 146 ++++++++++++++++++++++++++++++++++++
>  drivers/clk/meson/meson8b.h |   9 ++-
>  2 files changed, 154 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> index 0b9353d8d4fd..748552c5f6c8 100644
> --- a/drivers/clk/meson/meson8b.c
> +++ b/drivers/clk/meson/meson8b.c
> @@ -1573,6 +1573,135 @@ static struct clk_regmap meson8b_hdmi_sys = {
>  	},
>  };
>  
> +/*
> + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
> + * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
> + * has mali_0 and no glitch-free mux.
> + */
> +static const char * const meson8b_mali_0_1_parent_names[] = {
> +	"xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3",
> +	"fclk_div5"
> +};
> +
> +static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
> +
> +static struct clk_regmap meson8b_mali_0_sel = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_MALI_CLK_CNTL,
> +		.mask = 0x7,
> +		.shift = 9,
> +		.table = meson8b_mali_0_1_mux_table,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mali_0_sel",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_names = meson8b_mali_0_1_parent_names,
> +		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
> +		/*
> +		 * Don't propagate rate changes up because the only changeable
> +		 * parents are mpll1 and mpll2 but we need those for audio and
> +		 * RGMII (Ethernet). We don't want to change the audio or
> +		 * Ethernet clocks when setting the GPU frequency.
> +		 */
> +		.flags = 0,
> +	},
> +};
> +
> +static struct clk_regmap meson8b_mali_0_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_MALI_CLK_CNTL,
> +		.shift = 0,
> +		.width = 7,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mali_0_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_names = (const char *[]){ "mali_0_sel" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap meson8b_mali_0 = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_MALI_CLK_CNTL,
> +		.bit_idx = 8,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mali_0",
> +		.ops = &clk_regmap_gate_ops,
> +		.parent_names = (const char *[]){ "mali_0_div" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap meson8b_mali_1_sel = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_MALI_CLK_CNTL,
> +		.mask = 0x7,
> +		.shift = 25,
> +		.table = meson8b_mali_0_1_mux_table,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mali_1_sel",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_names = meson8b_mali_0_1_parent_names,
> +		.num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
> +		/*
> +		 * Don't propagate rate changes up because the only changeable
> +		 * parents are mpll1 and mpll2 but we need those for audio and
> +		 * RGMII (Ethernet). We don't want to change the audio or
> +		 * Ethernet clocks when setting the GPU frequency.
> +		 */
> +		.flags = 0,
> +	},
> +};
> +
> +static struct clk_regmap meson8b_mali_1_div = {
> +	.data = &(struct clk_regmap_div_data){
> +		.offset = HHI_MALI_CLK_CNTL,
> +		.shift = 16,
> +		.width = 7,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mali_1_div",
> +		.ops = &clk_regmap_divider_ops,
> +		.parent_names = (const char *[]){ "mali_1_sel" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap meson8b_mali_1 = {
> +	.data = &(struct clk_regmap_gate_data){
> +		.offset = HHI_MALI_CLK_CNTL,
> +		.bit_idx = 24,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mali_1",
> +		.ops = &clk_regmap_gate_ops,
> +		.parent_names = (const char *[]){ "mali_1_div" },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_regmap meson8b_mali = {
> +	.data = &(struct clk_regmap_mux_data){
> +		.offset = HHI_MALI_CLK_CNTL,
> +		.mask = 1,
> +		.shift = 31,
> +	},
> +	.hw.init = &(struct clk_init_data){
> +		.name = "mali",
> +		.ops = &clk_regmap_mux_ops,
> +		.parent_names = (const char *[]){ "mali_0", "mali_1" },
> +		.num_parents = 2,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
>  /* Everything Else (EE) domain gates */
>  
>  static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
> @@ -1833,6 +1962,9 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
>  		[CLKID_HDMI_SYS_SEL]	    = &meson8b_hdmi_sys_sel.hw,
>  		[CLKID_HDMI_SYS_DIV]	    = &meson8b_hdmi_sys_div.hw,
>  		[CLKID_HDMI_SYS]	    = &meson8b_hdmi_sys.hw,
> +		[CLKID_MALI_0_SEL]	    = &meson8b_mali_0_sel.hw,
> +		[CLKID_MALI_0_DIV]	    = &meson8b_mali_0_div.hw,
> +		[CLKID_MALI]		    = &meson8b_mali_0.hw,
>  		[CLK_NR_CLKS]		    = NULL,
>  	},
>  	.num = CLK_NR_CLKS,
> @@ -2012,6 +2144,13 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
>  		[CLKID_HDMI_SYS_SEL]	    = &meson8b_hdmi_sys_sel.hw,
>  		[CLKID_HDMI_SYS_DIV]	    = &meson8b_hdmi_sys_div.hw,
>  		[CLKID_HDMI_SYS]	    = &meson8b_hdmi_sys.hw,
> +		[CLKID_MALI_0_SEL]	    = &meson8b_mali_0_sel.hw,
> +		[CLKID_MALI_0_DIV]	    = &meson8b_mali_0_div.hw,
> +		[CLKID_MALI_0]		    = &meson8b_mali_0.hw,
> +		[CLKID_MALI_1_SEL]	    = &meson8b_mali_1_sel.hw,
> +		[CLKID_MALI_1_DIV]	    = &meson8b_mali_1_div.hw,
> +		[CLKID_MALI_1]		    = &meson8b_mali_1.hw,
> +		[CLKID_MALI]		    = &meson8b_mali.hw,
>  		[CLK_NR_CLKS]		    = NULL,
>  	},
>  	.num = CLK_NR_CLKS,
> @@ -2167,6 +2306,13 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
>  	&meson8b_hdmi_sys_sel,
>  	&meson8b_hdmi_sys_div,
>  	&meson8b_hdmi_sys,
> +	&meson8b_mali_0_sel,
> +	&meson8b_mali_0_div,
> +	&meson8b_mali_0,
> +	&meson8b_mali_1_sel,
> +	&meson8b_mali_1_div,
> +	&meson8b_mali_1,
> +	&meson8b_mali,
>  };
>  
>  static const struct meson8b_clk_reset_line {
> diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> index 87fba739af81..f212e2304ff5 100644
> --- a/drivers/clk/meson/meson8b.h
> +++ b/drivers/clk/meson/meson8b.h
> @@ -33,6 +33,7 @@
>  #define HHI_VID_CLK_CNTL2		0x194 /* 0x65 offset in data sheet */
>  #define HHI_VID_DIVIDER_CNTL		0x198 /* 0x66 offset in data sheet */
>  #define HHI_SYS_CPU_CLK_CNTL0		0x19c /* 0x67 offset in data sheet */
> +#define HHI_MALI_CLK_CNTL		0x1b0 /* 0x6c offset in data sheet */
>  #define HHI_HDMI_CLK_CNTL		0x1cc /* 0x73 offset in data sheet */
>  #define HHI_NAND_CLK_CNTL		0x25c /* 0x97 offset in data sheet */
>  #define HHI_MPLL_CNTL			0x280 /* 0xa0 offset in data sheet */
> @@ -139,8 +140,14 @@
>  #define CLKID_HDMI_SYS_SEL	172
>  #define CLKID_HDMI_SYS_DIV	173
>  #define CLKID_HDMI_SYS		174
> +#define CLKID_MALI_0_SEL	175
> +#define CLKID_MALI_0_DIV	176
> +#define CLKID_MALI_0		177
> +#define CLKID_MALI_1_SEL	178
> +#define CLKID_MALI_1_DIV	179
> +#define CLKID_MALI_1		180
>  
> -#define CLK_NR_CLKS		175
> +#define CLK_NR_CLKS		181
>  
>  /*
>   * include the CLKID and RESETID that have
> 

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>

Changing mali clock for Meson8 will be fun aswell !
How amlogic does that ? the only change the divider ?

Neil

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Re: [PATCH 3/5] clk: meson: meson8b: add the GPU clock tree

[Martin Blumenstingl]

Hi Neil,

On Tue, Dec 11, 2018 at 10:21 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> On 08/12/2018 18:12, Martin Blumenstingl wrote:
> > Add the GPU clock tree on Meson8, Meson8b and Meson8m2.
> >
> > The GPU clock tree on Meson8b and Meson8m2 is almost identical to the
> > one one GXBB:
> > - there's a glitch-free mux at HHI_MALI_CLK_CNTL[31]
> > - there are two identical parents for this mux: mali_0 and mali_1, each
> >   with a gate, divider and mux
> > - the parents of mali_0_sel and mali_1_sel are identical to GXBB except
> >   there's no GP0_PLL on these 32-bit SoCs
> >
> > Meson8 is different because it does not have the glitch-free mux.
> > Instead if only has the mali_0 clock tree. The parents of mali_0_sel are
> > identical to the ones on Meson8b and Meson8m2.
> >
> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > ---
> >  drivers/clk/meson/meson8b.c | 146 ++++++++++++++++++++++++++++++++++++
> >  drivers/clk/meson/meson8b.h |   9 ++-
> >  2 files changed, 154 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
> > index 0b9353d8d4fd..748552c5f6c8 100644
> > --- a/drivers/clk/meson/meson8b.c
> > +++ b/drivers/clk/meson/meson8b.c
> > @@ -1573,6 +1573,135 @@ static struct clk_regmap meson8b_hdmi_sys = {
> >       },
> >  };
> >
> > +/*
> > + * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
> > + * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
> > + * has mali_0 and no glitch-free mux.
> > + */
> > +static const char * const meson8b_mali_0_1_parent_names[] = {
> > +     "xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3",
> > +     "fclk_div5"
> > +};
> > +
> > +static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
> > +
> > +static struct clk_regmap meson8b_mali_0_sel = {
> > +     .data = &(struct clk_regmap_mux_data){
> > +             .offset = HHI_MALI_CLK_CNTL,
> > +             .mask = 0x7,
> > +             .shift = 9,
> > +             .table = meson8b_mali_0_1_mux_table,
> > +     },
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "mali_0_sel",
> > +             .ops = &clk_regmap_mux_ops,
> > +             .parent_names = meson8b_mali_0_1_parent_names,
> > +             .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
> > +             /*
> > +              * Don't propagate rate changes up because the only changeable
> > +              * parents are mpll1 and mpll2 but we need those for audio and
> > +              * RGMII (Ethernet). We don't want to change the audio or
> > +              * Ethernet clocks when setting the GPU frequency.
> > +              */
> > +             .flags = 0,
> > +     },
> > +};
> > +
> > +static struct clk_regmap meson8b_mali_0_div = {
> > +     .data = &(struct clk_regmap_div_data){
> > +             .offset = HHI_MALI_CLK_CNTL,
> > +             .shift = 0,
> > +             .width = 7,
> > +     },
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "mali_0_div",
> > +             .ops = &clk_regmap_divider_ops,
> > +             .parent_names = (const char *[]){ "mali_0_sel" },
> > +             .num_parents = 1,
> > +             .flags = CLK_SET_RATE_PARENT,
> > +     },
> > +};
> > +
> > +static struct clk_regmap meson8b_mali_0 = {
> > +     .data = &(struct clk_regmap_gate_data){
> > +             .offset = HHI_MALI_CLK_CNTL,
> > +             .bit_idx = 8,
> > +     },
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "mali_0",
> > +             .ops = &clk_regmap_gate_ops,
> > +             .parent_names = (const char *[]){ "mali_0_div" },
> > +             .num_parents = 1,
> > +             .flags = CLK_SET_RATE_PARENT,
> > +     },
> > +};
> > +
> > +static struct clk_regmap meson8b_mali_1_sel = {
> > +     .data = &(struct clk_regmap_mux_data){
> > +             .offset = HHI_MALI_CLK_CNTL,
> > +             .mask = 0x7,
> > +             .shift = 25,
> > +             .table = meson8b_mali_0_1_mux_table,
> > +     },
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "mali_1_sel",
> > +             .ops = &clk_regmap_mux_ops,
> > +             .parent_names = meson8b_mali_0_1_parent_names,
> > +             .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
> > +             /*
> > +              * Don't propagate rate changes up because the only changeable
> > +              * parents are mpll1 and mpll2 but we need those for audio and
> > +              * RGMII (Ethernet). We don't want to change the audio or
> > +              * Ethernet clocks when setting the GPU frequency.
> > +              */
> > +             .flags = 0,
> > +     },
> > +};
> > +
> > +static struct clk_regmap meson8b_mali_1_div = {
> > +     .data = &(struct clk_regmap_div_data){
> > +             .offset = HHI_MALI_CLK_CNTL,
> > +             .shift = 16,
> > +             .width = 7,
> > +     },
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "mali_1_div",
> > +             .ops = &clk_regmap_divider_ops,
> > +             .parent_names = (const char *[]){ "mali_1_sel" },
> > +             .num_parents = 1,
> > +             .flags = CLK_SET_RATE_PARENT,
> > +     },
> > +};
> > +
> > +static struct clk_regmap meson8b_mali_1 = {
> > +     .data = &(struct clk_regmap_gate_data){
> > +             .offset = HHI_MALI_CLK_CNTL,
> > +             .bit_idx = 24,
> > +     },
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "mali_1",
> > +             .ops = &clk_regmap_gate_ops,
> > +             .parent_names = (const char *[]){ "mali_1_div" },
> > +             .num_parents = 1,
> > +             .flags = CLK_SET_RATE_PARENT,
> > +     },
> > +};
> > +
> > +static struct clk_regmap meson8b_mali = {
> > +     .data = &(struct clk_regmap_mux_data){
> > +             .offset = HHI_MALI_CLK_CNTL,
> > +             .mask = 1,
> > +             .shift = 31,
> > +     },
> > +     .hw.init = &(struct clk_init_data){
> > +             .name = "mali",
> > +             .ops = &clk_regmap_mux_ops,
> > +             .parent_names = (const char *[]){ "mali_0", "mali_1" },
> > +             .num_parents = 2,
> > +             .flags = CLK_SET_RATE_PARENT,
> > +     },
> > +};
> > +
> >  /* Everything Else (EE) domain gates */
> >
> >  static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
> > @@ -1833,6 +1962,9 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
> >               [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
> >               [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
> >               [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
> > +             [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
> > +             [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
> > +             [CLKID_MALI]                = &meson8b_mali_0.hw,
> >               [CLK_NR_CLKS]               = NULL,
> >       },
> >       .num = CLK_NR_CLKS,
> > @@ -2012,6 +2144,13 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
> >               [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
> >               [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
> >               [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
> > +             [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
> > +             [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
> > +             [CLKID_MALI_0]              = &meson8b_mali_0.hw,
> > +             [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
> > +             [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
> > +             [CLKID_MALI_1]              = &meson8b_mali_1.hw,
> > +             [CLKID_MALI]                = &meson8b_mali.hw,
> >               [CLK_NR_CLKS]               = NULL,
> >       },
> >       .num = CLK_NR_CLKS,
> > @@ -2167,6 +2306,13 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
> >       &meson8b_hdmi_sys_sel,
> >       &meson8b_hdmi_sys_div,
> >       &meson8b_hdmi_sys,
> > +     &meson8b_mali_0_sel,
> > +     &meson8b_mali_0_div,
> > +     &meson8b_mali_0,
> > +     &meson8b_mali_1_sel,
> > +     &meson8b_mali_1_div,
> > +     &meson8b_mali_1,
> > +     &meson8b_mali,
> >  };
> >
> >  static const struct meson8b_clk_reset_line {
> > diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
> > index 87fba739af81..f212e2304ff5 100644
> > --- a/drivers/clk/meson/meson8b.h
> > +++ b/drivers/clk/meson/meson8b.h
> > @@ -33,6 +33,7 @@
> >  #define HHI_VID_CLK_CNTL2            0x194 /* 0x65 offset in data sheet */
> >  #define HHI_VID_DIVIDER_CNTL         0x198 /* 0x66 offset in data sheet */
> >  #define HHI_SYS_CPU_CLK_CNTL0                0x19c /* 0x67 offset in data sheet */
> > +#define HHI_MALI_CLK_CNTL            0x1b0 /* 0x6c offset in data sheet */
> >  #define HHI_HDMI_CLK_CNTL            0x1cc /* 0x73 offset in data sheet */
> >  #define HHI_NAND_CLK_CNTL            0x25c /* 0x97 offset in data sheet */
> >  #define HHI_MPLL_CNTL                        0x280 /* 0xa0 offset in data sheet */
> > @@ -139,8 +140,14 @@
> >  #define CLKID_HDMI_SYS_SEL   172
> >  #define CLKID_HDMI_SYS_DIV   173
> >  #define CLKID_HDMI_SYS               174
> > +#define CLKID_MALI_0_SEL     175
> > +#define CLKID_MALI_0_DIV     176
> > +#define CLKID_MALI_0         177
> > +#define CLKID_MALI_1_SEL     178
> > +#define CLKID_MALI_1_DIV     179
> > +#define CLKID_MALI_1         180
> >
> > -#define CLK_NR_CLKS          175
> > +#define CLK_NR_CLKS          181
> >
> >  /*
> >   * include the CLKID and RESETID that have
> >
>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
thank you for reviewing this!

> Changing mali clock for Meson8 will be fun aswell !
> How amlogic does that ? the only change the divider ?
I'm not sure how it works in practice, but the sequence is:
- spin_lock_irqsave (from mali_clock_critical)
- disable the clock
- change the divider and mux
- enable the clock again
- spin_unlock_irqrestore
(this is identical to the glitch-free mux setup except there's an
additional step for changing the mux before disabling the mali_0 clock
and after enabling the mali_0 clock again)

I learned the hard way that we can't access the Mali registers if the
clock is disabled.
so we need to be careful with this. my plan is to check the progress
of the lima driver from time to time - once there's frequency scaling
code I'll test it to see whether it works (or what I have to adjust)


Regards
Martin


[0] https://github.com/endlessm/linux-meson/blob/cd4096c3ff4eb5b8a8a5581bb46508601c5470dc/drivers/amlogic/gpu/mali/platform/mali_clock.c#L54

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[PATCH 4/5] ARM: dts: meson8: add the Mali-450 MP6 GPU

[Martin Blumenstingl]

Add the Mali-450 GPU and it's OPP table for the Meson8 and Meson8m2 (the
latter inherits meson8.dtsi).
These SoCs have a Mali-450 GPU with six pixel processors. The OPP table
is taken from the 3.10 vendor kernel which uses the following table:
  FCLK_DEV7 | 1,     /* 182.1 Mhz */
  FCLK_DEV4 | 1,     /* 318.7 Mhz */
  FCLK_DEV3 | 1,     /* 425 Mhz */
  FCLK_DEV5 | 0,     /* 510 Mhz */
  FCLK_DEV4 | 0,     /* 637.5 Mhz */
This describes the mux (FCLK_DEVx) and a 0-based divider in the clock
controller. "FCLK" is "fixed_pll" which is running at 2550MHz.
The "turbo" setting is described by "turbo_clock = 4" where 4 is the
index of the table above.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8.dtsi | 58 +++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 3fd8260eba92..1ea5a36c5040 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -166,6 +166,32 @@
 		};
 	};
 
+	gpu_opp_table: gpu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-182150000 {
+			opp-hz = /bits/ 64 <182150000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-318750000 {
+			opp-hz = /bits/ 64 <318750000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-425000000 {
+			opp-hz = /bits/ 64 <425000000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-510000000 {
+			opp-hz = /bits/ 64 <510000000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-637500000 {
+			opp-hz = /bits/ 64 <637500000>;
+			opp-microvolt = <1150000>;
+			turbo-mode;
+		};
+	};
+
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
@@ -208,6 +234,38 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0xd0000000 0x200000>;
+
+		mali: gpu@c0000 {
+			compatible = "amlogic,meson8-mali", "arm,mali-450";
+			reg = <0xc0000 0x40000>;
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gp", "gpmmu", "pp", "pmu",
+					  "pp0", "ppmmu0", "pp1", "ppmmu1",
+					  "pp2", "ppmmu2", "pp4", "ppmmu4",
+					  "pp5", "ppmmu5", "pp6", "ppmmu6";
+			resets = <&reset RESET_MALI>;
+			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+			clock-names = "bus", "core";
+			operating-points-v2 = <&gpu_opp_table>;
+			switch-delay = <0xffff>;
+		};
 	};
 }; /* end of / */
 
-- 
2.19.2


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[PATCH 5/5] ARM: dts: meson8b: add the Mali-450 MP2 GPU

[Martin Blumenstingl]

Add the Mali-450 GPU and it's OPP table for Meson8. The GPU uses two
pixel processors in this configuration. The OPP table is taken from the
3.10 vendor kernel which uses the following table:
  FCLK_DEV5 | 1,     /* 255 Mhz */
  FCLK_DEV7 | 0,     /* 364 Mhz */
  FCLK_DEV3 | 1,     /* 425 Mhz */
  FCLK_DEV5 | 0,     /* 510 Mhz */
  FCLK_DEV4 | 0,     /* 637.5 Mhz */
This describes the mux (FCLK_DEVx) and a 0-based divider in the clock
controller. "FCLK" is "fixed_pll" which is running at 2550MHz.
The "turbo" setting is described by "turbo_clock = 4" where 4 is the
index of the table above.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 46 ++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 5d036842c355..dd498e681939 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -158,6 +158,32 @@
 		};
 	};
 
+	gpu_opp_table: gpu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-255000000 {
+			opp-hz = /bits/ 64 <255000000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-364300000 {
+			opp-hz = /bits/ 64 <364300000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-425000000 {
+			opp-hz = /bits/ 64 <425000000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-510000000 {
+			opp-hz = /bits/ 64 <510000000>;
+			opp-microvolt = <1150000>;
+		};
+		opp-637500000 {
+			opp-hz = /bits/ 64 <637500000>;
+			opp-microvolt = <1150000>;
+			turbo-mode;
+		};
+	};
+
 	pmu {
 		compatible = "arm,cortex-a5-pmu";
 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
@@ -185,6 +211,26 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0xd0000000 0x200000>;
+
+		mali: gpu@c0000 {
+			compatible = "amlogic,meson8b-mali", "arm,mali-450";
+			reg = <0xc0000 0x40000>;
+			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gp", "gpmmu", "pp", "pmu",
+					  "pp0", "ppmmu0", "pp1", "ppmmu1";
+			resets = <&reset RESET_MALI>;
+			clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
+			clock-names = "bus", "core";
+			operating-points-v2 = <&gpu_opp_table>;
+			switch-delay = <0xffff>;
+		};
 	};
 }; /* end of / */
 
-- 
2.19.2


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Re: [PATCH 0/5] Meson (32-bit): add support for the Mali GPU

[Neil Armstrong]

On 08/12/2018 18:12, Martin Blumenstingl wrote:
> This series adds support for the Mali-450 GPU on Meson8 and Meson8b.
> Meson6 uses a Mali-400 GPU but since we don't have a clock driver (and
> I don't have a device for testing) Meson6 is left out in this series.
> 
> Meson8 uses a Mali-450 MP6 with six pixel processors. Meson8b (as
> cost-reduced SoC) uses a Mali-450 MP2 with two pixel processors.
> I tested both using the open source lima driver and a patched mesa
> from the lima project as well. Since we don't have display support
> on the 32-bit SoCs I used off-screen rendering as described in [0].
> The result is (for example): [1]
> 
> The bootloader (at least on my boards) leaves the Mali clock disabled
> by default. The board crashes when trying to access the Mali registers
> with the "core" clock disabled.
> Thus this series also implements the required clock driver changes. The
> Mali clock tree on Meson8b and Meson8m2 is almost identical to the one
> on GXBB (see the description of patch #3 for more details). Only Meson8
> is slightly different as it doesn't have a glitch-free mux. Patch #2
> prepares the meson8b clock driver so we can have different clocks per
> SoC.
> 
> Dependencies:
> - the .dts changes depend on my other series "ARM: dts: meson: add the
>   APB/APB2 busses" from [2]
> - the .dts changes from this series have no compile-time dependency on
>   the clock driver changes because CLKID_MALI was defined in the
>   dt-bindings since the first version of the clock driver (but it was
>   not used until now).
> - the .dts changes from this series have a runtime dependency on the
>   clock driver changes (also from this series) if you have a kernel
>   patched with the lima driver (without the lima driver there's no
>   runtime dependency)
> 
> Other notes:
> By default the GPU runs off the XTAL clock (24MHz). The lima driver
> currently does not update the GPU clock rate. Different frequencies
> have to be requested by adding the following properties to the Mali
> GPU node (to run it at 510MHz for example):
>   assigned-clocks = <&clkc CLKID_MALI>;
>   assigned-clock-rates = <510000000>;
> 
> 
> [0] https://gitlab.freedesktop.org/lima/web/wikis/home
> [1] https://abload.de/img/dump0myic0.png
> [2] https://patchwork.kernel.org/cover/10719445/
> 
> 
> Martin Blumenstingl (5):
>   dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b
>     compatible
>   clk: meson: meson8b: use a separate clock table for Meson8
>   clk: meson: meson8b: add the GPU clock tree
>   ARM: dts: meson8: add the Mali-450 MP6 GPU
>   ARM: dts: meson8b: add the Mali-450 MP2 GPU
> 
>  .../bindings/gpu/arm,mali-utgard.txt          |   6 +
>  arch/arm/boot/dts/meson8.dtsi                 |  58 +++
>  arch/arm/boot/dts/meson8b.dtsi                |  46 +++
>  drivers/clk/meson/meson8b.c                   | 349 +++++++++++++++++-
>  drivers/clk/meson/meson8b.h                   |   9 +-
>  5 files changed, 461 insertions(+), 7 deletions(-)
> 

Applied patches 2 & 3 to next/drivers for Linux 5.1

Kevin, have fun with the other patches !

Neil

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Re: [PATCH 0/5] Meson (32-bit): add support for the Mali GPU

[Kevin Hilman]

Neil Armstrong <narmstrong@baylibre.com> writes:

> On 08/12/2018 18:12, Martin Blumenstingl wrote:
>> This series adds support for the Mali-450 GPU on Meson8 and Meson8b.
>> Meson6 uses a Mali-400 GPU but since we don't have a clock driver (and
>> I don't have a device for testing) Meson6 is left out in this series.
>> 
>> Meson8 uses a Mali-450 MP6 with six pixel processors. Meson8b (as
>> cost-reduced SoC) uses a Mali-450 MP2 with two pixel processors.
>> I tested both using the open source lima driver and a patched mesa
>> from the lima project as well. Since we don't have display support
>> on the 32-bit SoCs I used off-screen rendering as described in [0].
>> The result is (for example): [1]
>> 
>> The bootloader (at least on my boards) leaves the Mali clock disabled
>> by default. The board crashes when trying to access the Mali registers
>> with the "core" clock disabled.
>> Thus this series also implements the required clock driver changes. The
>> Mali clock tree on Meson8b and Meson8m2 is almost identical to the one
>> on GXBB (see the description of patch #3 for more details). Only Meson8
>> is slightly different as it doesn't have a glitch-free mux. Patch #2
>> prepares the meson8b clock driver so we can have different clocks per
>> SoC.
>> 
>> Dependencies:
>> - the .dts changes depend on my other series "ARM: dts: meson: add the
>>   APB/APB2 busses" from [2]
>> - the .dts changes from this series have no compile-time dependency on
>>   the clock driver changes because CLKID_MALI was defined in the
>>   dt-bindings since the first version of the clock driver (but it was
>>   not used until now).
>> - the .dts changes from this series have a runtime dependency on the
>>   clock driver changes (also from this series) if you have a kernel
>>   patched with the lima driver (without the lima driver there's no
>>   runtime dependency)
>> 
>> Other notes:
>> By default the GPU runs off the XTAL clock (24MHz). The lima driver
>> currently does not update the GPU clock rate. Different frequencies
>> have to be requested by adding the following properties to the Mali
>> GPU node (to run it at 510MHz for example):
>>   assigned-clocks = <&clkc CLKID_MALI>;
>>   assigned-clock-rates = <510000000>;
>> 
>> 
>> [0] https://gitlab.freedesktop.org/lima/web/wikis/home
>> [1] https://abload.de/img/dump0myic0.png
>> [2] https://patchwork.kernel.org/cover/10719445/
>> 
>> 
>> Martin Blumenstingl (5):
>>   dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b
>>     compatible
>>   clk: meson: meson8b: use a separate clock table for Meson8
>>   clk: meson: meson8b: add the GPU clock tree
>>   ARM: dts: meson8: add the Mali-450 MP6 GPU
>>   ARM: dts: meson8b: add the Mali-450 MP2 GPU
>> 
>>  .../bindings/gpu/arm,mali-utgard.txt          |   6 +
>>  arch/arm/boot/dts/meson8.dtsi                 |  58 +++
>>  arch/arm/boot/dts/meson8b.dtsi                |  46 +++
>>  drivers/clk/meson/meson8b.c                   | 349 +++++++++++++++++-
>>  drivers/clk/meson/meson8b.h                   |   9 +-
>>  5 files changed, 461 insertions(+), 7 deletions(-)
>> 
>
> Applied patches 2 & 3 to next/drivers for Linux 5.1
>
> Kevin, have fun with the other patches !

Fun was had.

Patches 1, 4, 5 queued for v5.1 (branch: v5.1/dt)

Kevin


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