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* [PATCH v2] clk: meson: g12a: fix gp0 and hifi ranges
@ 2019-05-13 12:45 Jerome Brunet
  2019-05-14 18:13 ` Martin Blumenstingl
  0 siblings, 1 reply; 2+ messages in thread
From: Jerome Brunet @ 2019-05-13 12:45 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel, Jerome Brunet

While some SoC samples are able to lock with a PLL factor of 55, others
samples can't. ATM, a minimum of 60 appears to work on all the samples
I have tried.

Even with 60, it sometimes takes a long time for the PLL to eventually
lock. The documentation says that the minimum rate of these PLLs DCO
should be 3GHz, a factor of 125. Let's use that to be on the safe side.

With factor range changed, the PLL seems to lock quickly (enough) so far.
It is still unclear if the range was the only reason for the delay.

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
 drivers/clk/meson/g12a.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 206fafd299ea..d11606d5ddbd 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -463,7 +463,7 @@ static struct clk_regmap g12a_cpu_clk_trace = {
 };
 
 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
-	.min = 55,
+	.min = 125,
 	.max = 255,
 };
 
-- 
2.20.1


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^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH v2] clk: meson: g12a: fix gp0 and hifi ranges
  2019-05-13 12:45 [PATCH v2] clk: meson: g12a: fix gp0 and hifi ranges Jerome Brunet
@ 2019-05-14 18:13 ` Martin Blumenstingl
  0 siblings, 0 replies; 2+ messages in thread
From: Martin Blumenstingl @ 2019-05-14 18:13 UTC (permalink / raw)
  To: Jerome Brunet
  Cc: Kevin Hilman, linux-amlogic, linux-clk, linux-kernel, Neil Armstrong

On Mon, May 13, 2019 at 2:45 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> While some SoC samples are able to lock with a PLL factor of 55, others
> samples can't. ATM, a minimum of 60 appears to work on all the samples
> I have tried.
>
> Even with 60, it sometimes takes a long time for the PLL to eventually
> lock. The documentation says that the minimum rate of these PLLs DCO
> should be 3GHz, a factor of 125. Let's use that to be on the safe side.
>
> With factor range changed, the PLL seems to lock quickly (enough) so far.
> It is still unclear if the range was the only reason for the delay.
>
> Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
this matches with what Amlogic does in their 4.9 vendor kernel from
buildroot-openlinux-A113-201901:
$ grep -P "\tPLL_RATE" kernel/aml-4.9/drivers/amlogic/clk/g12a/g12a.h
| cut -d',' -f2 | tr -s " " | sort -u | head -n5
 125
 126
 128
 129
 132

based on that:
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

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2019-05-13 12:45 [PATCH v2] clk: meson: g12a: fix gp0 and hifi ranges Jerome Brunet
2019-05-14 18:13 ` Martin Blumenstingl

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