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To: Neil Armstrong X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200723_111426_733917_D1977A96 X-CRM114-Status: GOOD ( 18.29 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , Kevin Hilman , Rob Herring , linux-amlogic@lists.infradead.org, linux-arm-kernel , Jerome Brunet Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Hi Neil, On Thu, 23 Jul 2020 at 18:36, Neil Armstrong wrote: > > Hi Anand, > > On 23/07/2020 12:49, Anand Moon wrote: > > Hi Neil / Martin / Jerome / Kevin. > > > > I am a bit investigating the reset controller for the Amlogic SoC board. > > Each of thes reset controllers have different reset IP features. > > So we should map the reset controller to appropriate IP nodes > > in the DTS to make this work. > > Correct support is already done for Meson8/8b/GXL/GXBB/G12A/A1. > > Can you specify which features are missing ? Yes, the reset controller is working fine. Currently we have only one reset controller _reset-controller@1004_ But what observation is that we could have different reset controller reset-controller@1004 |--22 Sys_cpu_capb3 |--21 Dos_capb3 |--20 Mali_capb3 |--19 Hdmitx_capb3 |--18 Nand_capb3 |--17 Capb3_decode |--16 Gic reset-controller@1008 |--14 Sd_emmc_c |--13 Sd_emmc_b |--12 Sd_emmc_a |--11 Ethernet |--02 USB_OTG reset-controllet@4410 |--8 Audio DAC |--6 AHB BRIDGE CNTL |--5 tvfe |--4 AIFIFO |--3 Sys_cpu_bvci |--2 EFUSE |--1 SYS CPU |--0 Ring oscillator reset-controller@4414 |--15 I2C_Master 1 |--14 I2C_Master 2 |--33 VENCL |--12 VDI6 |--10 RTC |--9 VDAC This is what I would like to make it work. -Anand > > > > > Following are the reset controller reg ip blocks as per the Datasheet > > Datasheet :- S805_Datasheet V0.8 20150126 > > Datasheet :- S905X_Datasheet V0.3 20170314publicversion-Wesion > > On GXBB / GLX > > RESET_REGISTER ----> 0xc11004404 > > RESET1_REGISTER ----> 0xc11004408 > > RESET2_REGISTER ----> 0xc1100440c > > RESET3_REGISTER ----> 0xc11004410 > > RESET4_REGISTER ----> 0xc11004414 > > RESET5_REGISTER ----> 0xc1100441c > > RESET6_REGISTER ----> 0xc11004420 > > > > DataSheet - S922X_Public_Datasheet_V0.2-Hardkernel.pdf > > G12B / S905X3 > > RESET0_REGISTER ---> 0xFFD01004 > > RESET1_REGISTER ---> 0xFFD01008 > > RESET2_REGISTER ---> 0xFFD0100C > > RESET3_REGISTER ---> 0xFFD01010 > > RESET4_REGISTER ---> 0xFFD01014 > > RESET5_REGISTER ---> 0xFFD0101c > > RESET7_REGISTER ---> 0xFFD01020 > > > > Each of the reset controllers have some different bit fields, > > For that we need to have reset binding macros accordingly. > > It's a documentation issue, the register layout is the same from Meson8 > to G12A. > > Neil > > > > > Please share your thoughts and If you have some inputs or > > another approach please let me know. > > I just want your feedback before preparing > > and submitting some patches. > > > > Sorry my English is a bit poor to express hope you > > will understand what changes I am proposing. > > > > -Anand > > > _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic