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Subject: Re: [RFC, PATCHv1 15/28] x86: detect 5-level paging support
From: hpa@zytor.com
Date: Thu, 15 Dec 2016 12:52:24 -0800
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Sender: linux-arch-owner@vger.kernel.org
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To: Andi Kleen <ak@linux.intel.com>, Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>, "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>, Andrew Morton <akpm@linux-foundation.org>, the arch/x86 maintainers <x86@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>, Arnd Bergmann <arnd@arndb.de>, Dave Hansen <dave.hansen@intel.com>, Andy Lutomirski <luto@amacapital.net>, "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>, linux-mm <linux-mm@kvack.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Message-ID: <20161215205224.psx1zBoZ6sE1PIFmNuw_eFS2-mSa99L8pYP3_LbF5vY@z>

On December 15, 2016 11:20:17 AM PST, Andi Kleen <ak@linux.intel.com> wrote:
>
>The code is not calling CPUID in any performance critical path, only
>at initialization. So any discussion about saving a few instructions
>is a complete waste of time.
>
>-Andi

Sort of.  The BIOS boot code is very space-constrained for certain legacy bootloaders to continue to work.  The BIOS boot code proper does not need PIC.

However, the existing .ifnc solution already takes care of it, so it doesn't matter.
-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.